Hello,
I'm a newbie at generating SDC file. I'd like to find out the proper way to constraint a differential input clock. I have a diffential input clock with the signal names: CLK500+, CLK500-. The frequency is 500 MHz. These clock signals enter the FPGA as inputs to an internal differential buffer. The output of the differntial buffer is called CLK500. This CLK500 signal is one of the inputs to a clock MUX. The other input to the clock MUX is an internal PLL generated clock, frequency = 100 MHz. The ouput of the clock MUX is called CLK. Since the CLK signal is the end result of a few traverse clock paths, please show the proper way to constraint the "CLK" signal since it will be used as the global system clock.
Thank you,
Dave
