how to constrain low frequency clocks

[Altera_Forum]

Hi, everyone! 

 Again I encounter some problems in constraining very low frequency clocks.   I have a 15MHz input clock, then generate a 400Hz clock through counters, and further generate 100Hz, 40Hz,4Hz. All these low frequency signals are used as clocks.   I use "create_generated_clock" in SDC to constrain these clocks. But TimeQuest reports the following:   Warning: The period, rise edge, or fall edge of clock: fourhundred_hz_clk was found to be outside of the range of acceptable time values. The minimum acceptable time value is -2147483.647 and the maximum acceptable time value is 2147483.647. This clock will be ignored.  And all the subsequent clock assignments are ignored.   It seems that these clocks are below the lowest frequency range TimeQuest can handle. Maybe I could just ignore them in timing constraints, because they are running so slowly, and, I guess, will not cause a timing problem.   But if I delete the constraints, TimeQuest will report that it detects these signals are used as clocks without a constraint. So the full timing analysis is not available.   So what should I do?   Thanks!

[Altera_Forum]

--- Quote Start ---  Hi, everyone!   Again I encounter some problems in constraining very low frequency clocks.   I have a 15MHz input clock, then generate a 400Hz clock through counters, and further generate 100Hz, 40Hz,4Hz. All these low frequency signals are used as clocks.   I use "create_generated_clock" in SDC to constrain these clocks. But TimeQuest reports the following:   Warning: The period, rise edge, or fall edge of clock: fourhundred_hz_clk was found to be outside of the range of acceptable time values. The minimum acceptable time value is -2147483.647 and the maximum acceptable time value is 2147483.647. This clock will be ignored.  And all the subsequent clock assignments are ignored.   It seems that these clocks are below the lowest frequency range TimeQuest can handle. Maybe I could just ignore them in timing constraints, because they are running so slowly, and, I guess, will not cause a timing problem.   But if I delete the constraints, TimeQuest will report that it detects these signals are used as clocks without a constraint. So the full timing analysis is not available.   So what should I do?   Thanks!  --- Quote End ---    Hi,  I found the same issue with the classic timing analyzer. I would recommend you should use 15MHz as a clock and the slower signals as enable for your registers.   Kind regards  GPK

[Altera_Forum]

Hi wdshen, 

With so low frequency clocks I use the solution that pletz suggests. Use Fc=15MHz as the single main clock. Generate low frequencies through enable pulses 1/Fc long rather than usual clock square waves with a 50% duty cycle. Use Fc to clock all your devices and apply the enable pulses to devices which need to run slower.  Cris

[Altera_Forum]

Hi, Pletz and Cris72, 

 Thank you both. Yes, I know the usage of clock enable signal. If I write the code, I will also use it as a good synchronous design style.  But, since I am not the author of the code and the whole design is near the final stage, I am not supposed to change the code a lot. I wonder if there is a way to contrain the current design without changing the code. It is really a headache.:mad:

[Altera_Forum]

I suggest you lie about those clocks with very low frequencies and constrain them as if they had frequencies within TimeQuest's allowed range. 

 TimeQuest will allow for clocks as low as 100 kHz (at least).

[Altera_Forum]

--- Quote Start ---  I suggest you lie about those clocks with very low frequencies and constrain them as if they had frequencies within TimeQuest's allowed range.  TimeQuest will allow for clocks as low as 100 kHz (at least).  --- Quote End ---    Hi,  the suggesttion of rbugalho is a good one. There should be no clock speed problems occur, but Quartus will check setup and hold times.  Kind regards  GPK