Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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how to decrease compile time.

Altera_Forum
Honored Contributor II
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when a compile a project ,more than ten thousands lines. 

it used more than 3 hours. 

what i can do to avoid this. 

use good cpu? i used Xeon 3.4G 24G memory. 

optimize Quartus setting? but it not have palpable effects。 

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Altera_Forum
Honored Contributor II
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What device is it? how full is the device? what effort level are you set to? have you set quartus to use multiple CPU cores? 

Things that increase compile time are: 

 

- More code 

- larger devices 

- larger % of chip used (I think if it goes over 70% full, compile times start to go up a lot) 

- tight timing constraints. 

- running out of ram (though 24G should be plenty) 

 

The basic answer is get used to it. Unless you get a faster machine, the more you add to a chip, the longer the compile takes. (with my current design, a single build takes 5.5hrs, and it always fails timing!)
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Altera_Forum
Honored Contributor II
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i used Stratix V A7,chip usew over 60%. 

i think I think this is inevitable. but compile time is too long.
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Altera_Forum
Honored Contributor II
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What is too long? 3 hours sounds pretty good for a stratix V.

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Altera_Forum
Honored Contributor II
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You can go to Tools > Advisors > Compilation Time Advisor and see if Quartus suggests anything interesting to decrease the compilation time.

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Altera_Forum
Honored Contributor II
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Firstly, Quartus II 13.0 has considerably lower compile time than prior versions. So try upgrading to the latest Quartus version if you haven't already. 

 

Secondly, try consulting the Quartus II Handbook - there's a chapter on compile time.  

 

Finally, make sure you've turned off all non-essential optimizations, such as Physical Synthesis or increased effort levels.
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