Showing results for

- Intel Community
- FPGAs and Programmable Solutions
- Intel® Quartus® Prime Software
- how to incorporate 2 cycles of latency

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Mute
- Printer Friendly Page

Highlighted
##

Altera_Forum

Valued Contributor III

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-17-2016
06:10 PM

927 Views

how to incorporate 2 cycles of latency

hello fellow vhdl coders

I have been away from VHDL for over 2 years and I have a question which I am struggling to complete. does anyone know how to incorporate 2 cycles of latency into my vhdl module were i have muxes between 11 buses and an 8 bit output here is the code i have so far. library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux is port( clk: in std_logic; A: in STD_LOGIC_vector(7 downto 0); B: in STD_LOGIC_vector(7 downto 0); C: in STD_LOGIC_vector(7 downto 0); D: in STD_LOGIC_vector(7 downto 0); E: in STD_LOGIC_vector(7 downto 0); F: in STD_LOGIC_vector(7 downto 0); G: in STD_LOGIC_vector(7 downto 0); H: in STD_LOGIC_vector(7 downto 0); I: in STD_LOGIC_vector(7 downto 0); J: in STD_LOGIC_vector(7 downto 0); K: in STD_LOGIC_vector(7 downto 0); S0: in std_LOGIC_vector(3 downto 0); Z: out STD_LOGIC_vector(7 downto 0) ); end mux; architecture func of mux is begin p: process(clk,A,B,C,D,E,F,G,H,I,J,K,S0) begin if(rising_edge(clk)) then case s0 is when "0001" => Z <= A; when "0010" => Z <= B; when "0011" => Z <= C; when "0100" => Z <= D; when "0101" => Z <= E; when "0110" => Z <= F; when "0111" => Z <= G; when "1000" => Z <= H; when "1001" => Z <= I; when "1010" => Z <= J; when "1011" => Z <= K; when others => Z <=A; end case; end if; end process; end func; I have tried to look through my notes when I took this class in university but i just understand how to do cycles of latency is there anyone who can help me out?
1 Reply

Highlighted
##

Altera_Forum

Valued Contributor III

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

11-17-2016
08:00 PM

8 Views

inside that process or in another clocked process write:

--z to be signal, not output z_1d <= z; z_2d <= z_1d; -- this should be outputFor more complete information about compiler optimizations, see our Optimization Notice.