how to keep hearchie during the analysis & synthesis

[Altera_Forum]

hello , 

i synthesize my design by running quartus analysis & synthesis then i generate the verilog quartus mapping file VQM to obtain a synthesized netlist. Unfortunetly the VQM generated is not a hierarchical netlist . So i need an option to conservate the hearchie during running analysis and synthesis. thank you for your help.

[Altera_Forum]

I thought Quartus II stopped generating .vqms? What are you using it for? There isn't anything Quartus generates after synthesis that is designed for other tools, besides simulation files(which are not .vqm files). If you really needed a hierarchical .vqm, I think Synplify creates them.

[Altera_Forum]

hello , 

quartus can generate vqm for third party tool such as amplify ,precision with commande quartus_eda  i use the vqm file in order to do the design partitionning before loading the bitstreams on FPGAs. so i 'am looking for a hierarchical generated vqm file .