Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15059 Discussions

i am getting error as fitter cannot place one io_pll, cannot find a location with io_tile_lock_id of 77. this error i am getting in quartus prime 18.0. can any one help how to solve this problem

AC1
Beginner
1,752 Views
0 Kudos
3 Replies
AnandRaj_S_Intel
Employee
112 Views

Hi,

 

Can you elaborate on the steps.

  1. Which edition have you used?
  2. Can you share your design?

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

AC1
Beginner
112 Views

Hello,

i am using quartus 18.0.

i am using jesd, pcie,ddr, nand and ethernet in my interface

 

AnandRaj_S_Intel
Employee
112 Views

Hi,

 

I have tried to recreate the issue but not succeeded.

  1. I know you are using 18.0, I have asked you about the edition(Pro or Std)?
  2. You can share the design if possible.

Or to Debug the design

  1. Can you remove the IO PLL from design and compile design and check.
  2. Recheck the IP interface/ connections.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

 

Reply