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krond
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06-06-2020
11:19 PM
107 Views
i can't run my simulation, there is this error message. i can't really understand what is this
Determining the location of the ModelSim executable...
Using: c:/users/noone/desktop/modelsim_ase/win32aloem/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off displaencoder123 -c displaencoder123 --vector_source="C:/Users/noone/Documents/ETEC-122/Waveform.vwf" --testbench_file="C:/Users/noone/Documents/ETEC-122/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Sat Jun 06 19:16:39 2020
Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off displaencoder123 -c displaencoder123 --vector_source=C:/Users/noone/Documents/ETEC-122/Waveform.vwf --testbench_file=C:/Users/noone/Documents/ETEC-122/simulation/qsim/Waveform.vwf.vt
Info (201000): Generated Verilog Test Bench File C:/Users/noone/Documents/ETEC-122/simulation/qsim/Waveform.vwf.vt for simulation
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4776 megabytes
Info: Processing ended: Sat Jun 06 19:16:41 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="C:/Users/noone/Documents/ETEC-122/simulation/qsim/" displaencoder123 -c displaencoder123
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Sat Jun 06 19:16:42 2020
Info: Command: quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation=on --tool=modelsim_oem --format=verilog --output_directory=C:/Users/noone/Documents/ETEC-122/simulation/qsim/ displaencoder123 -c displaencoder123
Info (204019): Generated file displaencoder123.vo in folder "C:/Users/noone/Documents/ETEC-122/simulation/qsim//" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4783 megabytes
Info: Processing ended: Sat Jun 06 19:16:43 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
C:/Users/noone/Documents/ETEC-122/simulation/qsim/displaencoder123.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/users/noone/desktop/modelsim_ase/win32aloem//vsim -c -do displaencoder123.do
Reading C:/Users/noone/Desktop/modelsim_ase/tcl/vsim/pref.tcl
# 10.3d
# do displaencoder123.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014
# Start time: 19:16:44 on Jun 06,2020
# vlog -work work displaencoder123.vo
# -- Compiling module displaencoder123
#
# Top level modules:
# displaencoder123
# End time: 19:16:44 on Jun 06,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014
# Start time: 19:16:44 on Jun 06,2020
# vlog -work work Waveform.vwf.vt
# -- Compiling module displaencoder123_vlg_sample_tst
# ** Error: Waveform.vwf.vt(31): near "-": syntax error, unexpected '-', expecting ')'
# End time: 19:16:44 on Jun 06,2020, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: c:/users/noone/desktop/modelsim_ase/win32aloem/vlog failed.
# Executing ONERROR command at macro ./displaencoder123.do line 4
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ShyanYewT_Intel
Employee
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06-09-2020
04:17 PM
85 Views
Could you try to open Waveform.vwf.vt with a text editor and try to understand which original waveform editor entry might show at line 31 and what's wrong with it?
For more complete information about compiler optimizations, see our Optimization Notice.