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Valued Contributor III
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i'm a bit confused

Hi!! 

 

I've try to program a 4-bit up/down counter that counts from 0...9! It will be used for an lcd to display the covered distance of a system. So I used a very easy way to implement it. There are only four D-FF with some additional logic. 

First of all, I programmed a Cyclone II (EP2C35) device and the counter doesn't work in the desired way. Afterwards I programmed a Cyclone (EP1C20) device with absolutly the same code and it works perfectly. The differences are only the pinning an the device itself.  

 

Are there anybody who have seen a similar problem?? Where is the problem?? 

 

Thanks for the reply!!!
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Valued Contributor III
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I would recommend you start with the basic questions: 

 

Are you making correct device and pin related assignments while you compile your project for Cyclone II in Quartus II?  

Are you downloading correct SOF/POF file in the device (Cyclone II) for testing? 

Is your FPGA (Cyclone II) being correctly powered up? 

Is your FPGA (Cyclone II) getting correctly configured (config_done goes high)? 

Is your FPGA (Cyclone II) getting correct clock and other control signals? 

 

It would also help if you mention which version of Quartus II and which board are you using for your development? 

 

-BD
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Valued Contributor III
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Cyron, you'better state your question clearly. For example, the errors are"......". 

We can't imagine them exactly sometimes. As BD said the problem may occur in your FPGA board or your operation of Quartus. 

Regards.
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Valued Contributor III
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firstly some answers: 

 

I use the ALTERA Cyclone II Development Kit, which is populated by the EP2C35F672C6N and a Terasic TREX C1 Multimedia Development Kit, which is populated by the EP1C6Q240C8. 

 

- the FPGA is powered up correctly 

- the FPGA gets cofigured in the required way 

- clock signals an other control signals are correct too 

 

Source Code (Verilog) 

-------------------------- 

// lsb 

DFF A1(.d((~q3 && ~q0 && ~dir) || (~q2 && ~q1 && ~q0 && ~dir) || (~q3 && ~q0 && dir) || (~q2 && ~q1 && ~q0 && dir)), .clk(clk), .clrn(rst), .q(q0)); 

 

 

DFF A2(.d((~q3 && q2 && ~q1 && ~q0 && ~dir) || (q3 && ~q2 && ~q1 && ~q0 && ~dir) || (~q3 && q1 && q0 && ~dir) || (~q3 && ~q1 && q0 && dir ) || (~q3 && q1 && ~q0 && dir)), .clrn(rst), .clk(clk), .q(q1)); 

 

 

DFF A3(.d(( q3 && ~q2 && ~q1 && ~q0 && ~dir) || (~q3 && q2 && q0 && ~dir) || (~q3 && q2 && q1 && ~dir) || (~q3 && ~q2 && q1 && q0 && dir) || (~q3 && q2 && ~q1 && dir) || (~q3 && q2 && ~q0 && dir)), .clrn(rst), .clk(clk), .q(q2)); 

 

//msb 

DFF A4(.d((~q3 && ~q2 && ~q1 && ~q0 && ~dir) || (q3 && ~q2 && ~q1 && q0 && ~dir) || (q3 && ~q2 && ~q1 && ~q0 && dir) || (~q3 && q2 && q1 && q0 && dir)), .clrn(rst), .clk(clk), .q(q3)); 

 

If I program the Cyclone with these code everything works fine. So it count from 0..9 (dir = 1) and from 9..0 (dir = 0). But the problem occurs when I use the Cyclone II device. It count first from 0..9 but after the first overflow, it counts only 0,3,6,9,0,... and so on. So the problem must be the Quartus software, because the source code is the same, the clock frequency is the same and all cofigure procedures are correct. Only the device and the pinning for the IO's are different. 

 

So were is the problem??
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Valued Contributor III
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I double checked the equations in modelsim. Cyclone I and II and using the same LUT masks (I have a Quartus 7.1) slightly different ordering, but equivalent. So barring something completely sinister it's not the software. 

 

I would follow BD's advice. Also check for silly things like contact bounce on the input switches, race conditions in the control signals, etc..
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Valued Contributor III
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Hi! 

 

i checked the equations with the quartus II simulator (Version 7.1) too. the simulations shows for both devices the same and correct function. but the reality isn't like the simulation.  

the input signals were generated from an internal pll and two counters which were used to scale the counting frequency once more down.  

 

how could i find out race conditions?? are there any usful tools to analyse some conditions the check situations like this?? 

 

i checked the control signals too. i think the development board would not be configurable and would not be able start after programming if an error of the control signal is present.  

 

is there anybody who can check my phenomenon for a "real" system too?? 

 

thanks for your responses!!!
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Valued Contributor III
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Since you are able to get the counter running first time, I am assuming that the pin assignments are correct. But it's worth verifying one more time for the Cyclone II device. If that is correct, then try to verify the board's connectivity. Try to run a simple code, which simply uses the clock that you are using for the counter and blinks the LED. If the LEDs get correct signals, then board must be OK.  

 

Also try to simulate the code in Quartus II simulator to see how it works for the Cyclone II device.  

 

Is it a design requirement to realize this counter using D flip-flops?
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Valued Contributor III
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Can I see the PLL / Clock divide counter scheme?  

 

Thanks
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Valued Contributor III
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If you want to realize the counter only, the Quartus II template for up/down counter looks like this: 

 

 

--- Quote Start ---  

// Quartus II Verilog Template 

// Binary up/down counter 

 

module binary_up_down_counter 

input clk, enable, count_up, reset, 

output reg [WIDTH-1:0] count 

); 

 

parameter WIDTH = 64; 

 

// Reset if needed, increment or decrement if counting is enabled 

always @ (posedge clk or posedge reset) 

begin 

if (reset) 

count <= 0; 

else if (enable == 1'b1) 

count <= count + (count_up ? 1 : -1); 

end 

 

endmodule 

--- Quote End ---  

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