Trouble using component..SOS

[Altera_Forum]

hello folks, 

I'm implementing a project on cyclone II board.For that, I've made my design files into an IP in the sopc builder. After the system gets generated, I'm seeing the avalon signals in the Pin assignment of the quartus 2 project. But I had assigned the signals to the respective avalon interface in the "New component".. What could be the trouble? the avalon pins are not supposed to show up in the pin assignment right? Please help..

[Altera_Forum]

Hi Fraiskir: 

 One possible issue is you have the pins defined as export. Also, what version of Quartus are you using, I know the SOPC system is different between quartus 6.x and 7.1, so there might be some issues there.  Sorry I can't be of more help. I've done several SOPC masters/slaves in Quartus 6.1 but haven't had a chance to play with 7.1 yet. (For SOPC builder)  Pete

[Altera_Forum]

Hello anakha, 

Nope. I'm not defining the pins as export. I have quartus version 6.1 and SOPC builder version 6.1.  Ok, here's the thing. I'm instantiating 3 components in the top level HDL, whose entity contains the avalon specific signals.I map those signals onto few components. Now, when i try creating a IP out of that entity, the system generation etc. works fine, so does the programmer, but these top level entity's port signals appear on the pin assignment, "unassigned".

[Altera_Forum]

--- Quote Start ---   Ok, here's the thing. I'm instantiating 3 components in the top level HDL, whose entity contains the avalon specific signals.  --- Quote End ---    I'm assuming you mean the top level SOPC system here, not the top level of the design (verilog/VHDL file)    --- Quote Start ---  I map those signals onto few components. Now, when i try creating a IP out of that entity, the system generation etc. works fine, so does the programmer, but these top level entity's port signals appear on the pin assignment, "unassigned".   --- Quote End ---    I'm grasping at straws here, but one thing I saw in the past if you ever changed a component, you needed to remove and re-add it into the SOPC system. Otherwise, it would sometimes not get the signals assign correctly:  IE: If you originally generated the component, then you modified it (Especially if you changed any component IO's, if you didn't remove it from the SOPC system sometimes it wouldn't pick up the pin changes. The System would build but then you would get errors similar to this.  To correct it, all you need to do is remove the component from the SOPC system, then add it back in, and re-connect it before generating.  Hope this helps. If not, it might be helpful to have a screen shot of the system and the component pin setup.  Pete

[Altera_Forum]

--- Quote Start ---  I'm assuming you mean the top level SOPC system here, not the top level of the design (verilog/VHDL file)  --- Quote End ---    It is the top level of the design and not SOPC. and I'm not changing anything in the design file once the IP is created.  here's the screen shot of the entity of my top-level-design file. I'm trying to create this into a component IP in sopc builder by mapping it onto avalon slave. http://www.kiranchandran.info/wp-content/uploads/2007/09/top-level-design.jpg (http://www.kiranchandran.info/wp-content/uploads/2007/09/top-level-design.jpg) and this is the sopc builder screen shot, my IP is surround_main. http://www.kiranchandran.info/wp-content/uploads/2007/09/sopc.jpg (http://www.kiranchandran.info/wp-content/uploads/2007/09/sopc.jpg)

[Altera_Forum]

Help PPL!!!

[Altera_Forum]

Refer to chapter 4 (SOPC Builder components) and 5 (Component Editor) of Quartus II v7.1 handbook volume 4 (SOPC Builder). If you are using different version of Quartus II, then look for the chapters with above heading to get the idea of pin mapping for avalon slave and generating/building custom components using component editor.

[Altera_Forum]

Yep, i've gone through all that and I'm doing exactly as is mentioned in the tutorials and literature.