Hi, I try to implement a Grey counter for CycloneII.
I'm using Quartus 7.1. I think the VHDL code, please see below,
is right. When I compile the code I get following error message:
Error: Node instance "\create_lsb:1:createbit" instantiates undefined entity "gray_1"
Does anybody know what I'm doing wrong?
Thanks for the help!
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration Top Level
ENTITY gray_n IS GENERIC(width: INTEGER :=3);
PORT(async_rst, clock : IN STD_LOGIC;
q : INOUT STD_LOGIC_VECTOR(width DOWNTO 0));
END gray_n;
-- Architecture Body
ARCHITECTURE archgray_n OF gray_n IS
component gray_1 is PORT ( arst, clk, qin, zin : IN STD_LOGIC;
qout : INOUT STD_LOGIC;
zout : OUT STD_LOGIC);
end component;
-- inner interconnection of 1-bit sections
signal z : STD_LOGIC_VECTOR(width DOWNTO 0);
-- auxiliary signal for MSB
signal qx : STD_LOGIC;
BEGIN
--less significant bits
create_lsb : FOR i IN 1 TO width-1 GENERATE
createbit : gray_1 PORT MAP (async_rst, clock,
q(i-1), z(i-1),
q(i), z(i));
end generate;
-- most sigificant bits
create_msb: gray_1 PORT MAP(async_rst, clock,
qx, z(width-1),
q(width), z(width));
--auxiliary signal for MSB
qx <= q(width-1) or q(width);
--parity bit generation
----------------------------------------------------------
process(async_rst, clock)
begin
if (async_rst ='1') then
q(0) <= '1';
elsif(clock'event and clock = '1') then
q(0) <= not q(0);
end if;
end process;
z(0) <= '1';
end archgray_n;
