implementation of don't care

Altera_Forum · ‎03-04-2015

Say I was given a function for four variables

f= product of maxterms(3,11,14)+ D(0,2,10,12)

The function's least cost implementation is x1+x2'+x3'

However, this does not take into don't care signals; is there any way to specify those signals?

Altera_Forum · ‎03-04-2015

ENTITY example1 IS

PORT (x1,x2,x3 : IN BIT;

f : OUT BIT);

END example1;

ARCHITECTURE LogicFunc OF example1 IS

BEGIN

f <= (x1 OR x2 OR x3);

END LogicFunc;

Altera_Forum · ‎03-04-2015

I dont really understand the question. On hardware, there is only '1' or '0'. Dont care can be used to tell the synthesisor to optimise the logic a bit better, but you got to be careful how you use the dont care value.