implementing primitives

[Altera_Forum]

I am new to vhdl; I tried to instantiate a dff 

 I put the following at the top: library altera; Use altera.altera_primitives_components.all;   and then in the architecture I put the following   xxx : dff  Port map(  d => Phases_in(1),   clk => Clock,   clrn => Reset,  prn => '1',  q => Phases(0)  );   I get this error   Error (10500): VHDL syntax error at Position_Encoder.vhd(121) near text "Port"; expecting "(", or "'", or "."    It is like it doesn't recognize it as an instantiation. I am using the web edition, is important.   Thanks jtg

[Altera_Forum]

You've only posted a snippet, not line 121. This will just be a syntax error.

[Altera_Forum]

line 121 is the one which has "port map" on it. 

If I remove the dffs from the code it compiles fine.

[Altera_Forum]

please post the entire file. I suspect the problem is elsewhere.

[Altera_Forum]

Library IEEE; 

Use IEEE.std_logic_1164.all; Use IEEE.numeric_std.all; library altera; Use altera.altera_primitives_components.all; ENTITY Position_Encoder IS  Port (  Reset: IN STD_LOGIC;  Index: IN STD_LOGIC;  Home : IN STD_LOGIC;  Clock: IN STD_LOGIC;  Phases_in: IN STD_LOGIC_VECTOR (1 downto 0);  Position: OUT INTEGER RANGE 0 to 500000;  Present_state: Out std_logic_vector (2 downto 0);  Error: BUFFER STD_LOGIC  );  END Position_Encoder;    -------------------------------------   ARCHITECTURE logic OF Position_Encoder IS TYPE State IS (state00, state01, state10, state11); SIGNAL pr_state, next_state : State; SIGNAL temp : integer range 0 to 500000; Signal Phases : std_logic_vector (1 downto 0);    BEGIN  PROCESS (Reset, Clock)  BEGIN  IF (Reset = '1')THEN  pr_state <= state00;  temp <= 10;  ELSIF (Clock'EVENT AND Clock = '1') THEN  CASE pr_state IS  WHEN state00 =>  Present_state <= "000";  IF (Phases = "00") THEN  pr_state <= state00;  Error <= '0';  ELSIF (Phases = "10") THEN  pr_state <= state10;  temp <= temp - 1;  Error <= '0';  ElsIF (Phases = "01") THEN  pr_state <= state01;  temp <= temp + 1;  Error <= '0';  ELSIF (Phases = "11") THEN  -- Error <= '1';  pr_state <= state00;  END IF;  WHEN state01 =>  Present_state <= "001";  IF (Phases = "01") THEN  pr_state <= state01;  Error <= '0';  ELSIF (Phases = "00") THEN  pr_state <= state00;  temp <= temp - 1;  -- Error <= '0';  ElsIF (Phases = "11") THEN  pr_state <= state11;  temp <= temp + 1;  Error <= '0';  ELSIF (Phases = "10") THEN  Error <= '1';  pr_state <= state01;  END IF;  WHEN state10 =>  Present_state <= "010";  IF (Phases = "10") THEN  pr_state <= state10;  Error <= '0';  ELSIF (Phases = "11") THEN  pr_state <= state11;  temp <= temp - 1;  Error <= '0';  ElsIF (Phases = "00") THEN  pr_state <= state00;  temp <= temp + 1;  Error <= '0';  ELSIF (Phases = "01") THEN  Error <= '1';  pr_state <= state10;  END IF;  WHEN state11 =>  Present_state <= "011";  IF (Phases = "11") THEN  pr_state <= state11;  Error <= '0';  ELSIF (Phases = "01") THEN  pr_state <= state01;  Error <= '0';  temp <= temp - 1;  ElsIF (Phases = "10") THEN  pr_state <= state10;  temp <= temp + 1;  Error <= '0';  ELSIF (Phases = "00") THEN  Error <= '1';  pr_state <= state11;  END IF;  END CASE; --end: CASE pr_state IS  --temp <= temp + 1;  Position <= temp;  END IF; --end: ELSIF (Clock'EVENT AND Clock = '1') THEN   xxx : dff  Port map(  d => Phases_in(1),   clk => Clock,   clrn => Reset,  prn => '1',  q => Phases(0)  );   delay_2 : dff  port map (  d => Phases_in(1),   clk => Clock,   clrn => Reset,  prn => '1',  q => Phases(1)  );  end process;   END logic;     Here it is. I appreciate your taking a look.

[Altera_Forum]

you cant instantiate anything inside a process. Instantiation has to be done outside a process.

[Altera_Forum]

Thanks alot. I appreciate your help. Life is good ... well better now. 

 jtg