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io pin assignment

Altera_Forum
Honored Contributor II
‎02-24-2011 03:17 PM
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Hi, 

I have added an IP core to the sopc builder. generated system no errors. (quartus 8.1) Now trying to connect its output ports which are only 2 lines clock and data to fpga pins. there is also a top level verilog file in quartus, which has io ports defined in it.  

Will i have to enter the ipcore's ports in that top level file or can i do it through pin assignment editor? There are other interfaces also defined in the top level file and pin planner generated file is not the same as this top level file. 

please help. thanks.
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Altera_Forum
Honored Contributor II
‎02-24-2011 05:59 PM
390 Views

i'm not quite clear on what's going on. you should have instantiated your SOPC Builder in your top level Verilog file (or in one of the instantiated modules). this instantiation should map the outputs from your SOPC Builder system to outputs of the top level module 

 

you will still have to assign the I/O locations and specs in Pin Planner/Assignment Editor in addition to "porting" the outputs to the top level of the design
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