ModelSim error

[Altera_Forum]

Hi everyone... 

 I want to ask a question, In my VHDL design I manage to compile and simulate it using quartus simulator, it goes well. But when I tried to simulate it in ModelSim, I got an error messages like this :  # ERROR! Vector Mismatch for output port done :: @time = 10 ns# Expected value = 0# Real value = U# ERROR! Vector Mismatch for output port P :: @time = 10 ns# Expected value = 0000000000000000# Real value = UUUUUUUUUUUUUUUU# ERROR! Vector Mismatch for output port P :: @time = 75 ns# Expected value = 1110110000000000# Real value = UUUUUUUUUUUUUUUU  What does this mean?

[Altera_Forum]

Being a begginer I would be grateful if anyone can verify the fact that code simulated in Quartus not necessarily simulates in ModelSim. Why is this so?

[Altera_Forum]

Modelsim requires initial values that are read in the design to be set to a known value of 0 or 1. Otherwise you get X or U that could propagate through logic. e.g. counters may start unknown and addition to unknown stays unknown. Similarly accumulators may go for ever unknown.

[Altera_Forum]

I assumed that I did that. Based on vaweform file (where I specified inputs) I got the testbench file. That testbench was used in ModelSim and I got posted error. What am I doing wrong?

[Altera_Forum]

Does your design have "done" and "P" signals default values specified, e.g. with reset logic? Important thing to know is that Modelsim assigns unspecified values to signals that hasn't been properly initialized by user, whereas Quartus assigns such signals a value of "0" by default. 

Can you attach testbench file?

[Altera_Forum]

Thanks for the replies. 

Upon closer inspection of warning comments in the Quartus II simulator tool I get following warning: Could this be somehow connected to the problems in ModelSim?      Warning: Cannot find channels in vector source file for the following output ports - channels are required for VCD file generation for PowerPlay Power Analyzer