library ieee;
use ieee.std_logic_1164.all;
entity mux1 is
port (
a,b:in std_logic_vector(7 downto 0);
sel:in std_logic_vector(1 downto 0);
c :out std_logic_vector (7 downto 0)
);
end mux1;
architecture example of mux1 is
begin
process(a,b,s)
begin
if (sel="00")then
c<="00000000"
elsif (sel="01")then
c<=a;
elsif (sel="10")then
c<=b;
else
c<=(others=>'Z');
end if;
end process;
end example ;
Error (10500): VHDL syntax error at mux1.vhd(16) near text "elsif"; expecting ";"
can you give a advice .thank you very much!
