latency in 1 port ram help

Altera_Forum · ‎11-20-2016

Hello,

I am new to vhdl. I am using the on chip RAM and the built in integer comparator to do something as following:

1. memory_a & memory_b both are the on chip ram with size 32 bit * 128 with some initial data.

2. given addr_a and addr_b to each memory and get the output of the ram q_a, q_b

3. input q_a, q_b into comparator to compare these two number.

but I find out that due to piplining of the ram, there is 2 clock cycle delay between input address and get the output of RAM, which will cause comparator get the previous state of RAM output as the current input.

I am wondering if there is any way to solve this. (maybe delay the comparator for 2 cycles?)

Or how to design the circuit according to this 2 clock cycle latency?

I know this question might be stupid, but i really need help. Manky thanks.

Altera_Forum · ‎11-21-2016

Hi,

yes, there will always be a delay. However, all you have to do is to "disable" the comparator during the time that the data is invalid.

That's no particular VHDL trick, it's just a thing you have to get use to when doing hardware (it gets worse with SDRAM chips, where the timing can differ when you hit a refresh cycle...).

Here's some example code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example is
	port(
		clk, rst: in std_logic;
		test_request: in std_logic;
		test_address: in std_logic_vector(6 downto 0);
		test_pass: out std_logic;
		test_fail: out std_logic);
		
end entity;
architecture rtl of example is
	
	component my_memory is
		port(
			address: in std_logic_vector (6 downto 0);
			clock: in std_logic;
			data: in std_logic_vector (31 downto 0);
			wren: in std_logic;
			q: out std_logic_vector (31 downto 0));
	end component;
	
	signal data_a, data_b: std_logic_vector (31 downto 0);
	signal delay1, delay2: std_logic;
	
begin
	
	
	
	my_memory_inst_a: my_memory
		port map(
			address => test_address,
			clock => clk,
			data => (others => '-'),
			wren => '0', -- never write (memory is pre-initialized)
			q => data_a);
	
	
	
	my_memory_inst_b: my_memory
		port map(
			address => test_address,
			clock => clk,
			data => (others => '-'),
			wren => '0', -- never write (memory is pre-initialized)
			q => data_b);
	
	
	
	process(rst, clk) is
	begin
		if(rst = '1') then
			delay1 <= '0';
			delay2 <= '0';
		elsif(rising_edge(clk)) then
			
			-- delay request signal
			delay1 <= test_request;
			delay2 <= delay1;
			
		end if;
	end process;
	
	
	
	process(rst, clk) is
	begin
		if(rst = '1') then
			test_pass <= '0';
			test_fail <= '0';
		elsif(rising_edge(clk)) then
			
			-- default assignments
			test_pass <= '0';
			test_fail <= '0';
			
			-- compare data
			if(delay2 = '1') then -- note that delay2 is in sync with the read data
				if(data_a = data_b) then
					test_pass <= '1';
				else
					test_fail <= '1';
				end if;
			end if;
			
		end if;
	end process;
	
	
	
end architecture;

The idea is that you assert the address ("test_address") you want to compare, while in the same clock cycle setting "test_request" to '1'. By delaying the request signal by two clocks, "delay2" will be '1' exactly two cycles after the data was requested, which is the exact same clock cycle when the data is returned from the RAM (in your case, you said it's two clocks).

That's just some example code to give you the idea. I didn't compile it, but it should work, maybe there are a few syntax errors.

Best regards,

GooGooCluster

Altera_Forum · ‎11-21-2016

Thanks a lot of your help!

I am also wondering is that a common things for doing hardware to add a some extra processes to dealing with the delay?

Altera_Forum · ‎11-22-2016

Hi,

yes, it is quite common to delay signals to be in sync with others. However, sometimes it's not exactly as obvious as having a delayed signal. Sometimes you just add another state to a state-machine, which equals a single delay. Sometimes you implement a FIFO, so that an uncertain delay can be compensated for. And, needless to say, you're quite happy if you find an alternative solution that works without additional delay :-)

Best regards,

GooGooCluster