Hi. I'm new to VHDL. I want to write a code to get the inverse of matrix. My code ispackage type_m is type row is array (0 to 1) of std_logic_vector (15 downto 0); type matrix is array (0 to 1) of row; end package type_m; entity mat_inv is port ( a : in matrix; b: out matrix); end mat_inv; architecture Behavioral of mat_inv is signal det: STD_LOGIC_VECTOR; begin det <= (a(0,0) * a(1,1)) - (a(1,0) * a(0,1)); det <= abs(std_logic_vector(det)); b(0,0) <= (1/det)*a(1,1); b(0,1) <= (1/det)*(-a(0,1)); b(1,0) <= (1/det)*(-a(1,0)); b(1,1) <= (1/det)*a(0,0); end Behavioral; But at first I get error that b is not declared. If I comment it, then it says det and std_logic_vector is not declared!!!!! I added these libraries: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.all; Thank you :)
So there are a several problems here.1. You didnt give det a size 2. You declared the array types as 1D arrays, but you're trying to access the elements as 2d arrays. You should write: det <= (a(0)(0) * a(1)(1)) - (a(1)(0) * a(0)(1)); 3. Your 2nd assignment to det is going to cause multiple drivers on det, giving you Xs in simulation. Each signal can only have a single driver. This is not software and your code all assigns values in parrallel 4. Using dividers really requires the use of a divider IP core. Using an in-line divide will create a really really slow circuit. 5. You are going to hit overflow and clipping issues. Nbits * Nbits gives a 2N bit number. You're trying to assign a 48 bit number (assuming det is 32 bits and a is 16 bits) to a 16 bit output output. 6. More a style point - you should not do arithmatic with std_logic_vectors. They are not meant to represent numbers, just a collection of bits. std_logic_unsigned library is a non-standard library. You should use unsigned/signed from the numeric_std package.