matrix multiplexing problem

[Altera_Forum]

Hello everyone 

 I working on "image processing" project that implemented on DE2-70 board.  The project based on 2D convolution between image and convolution kernel.  The result presented on PC screen using VGA.  A few days ago i got good results, and now i want to add option to select different "kernels" by using SW on DE2-70 board. To do this, i tried to use MUX in all know ways (IF, CASE, WHEN, WITH SELECT).  But unfortunately every time i get the same warning messages and my project stop working  Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following LCELL buffer node(s): Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_X:C2|lpm_mult:Mult5|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_X:C2|lpm_mult:Mult5|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_Y:C1|lpm_mult:Mult3|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_Y:C1|lpm_mult:Mult3|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_Y:C1|lpm_mult:Mult1|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_Y:C1|lpm_mult:Mult1|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_X:C2|lpm_mult:Mult15|mult_fus:auto_generated|le5a" Warning (14320): Synthesized away node "system_edge:SOBEL|conv_2d_X:C2|lpm_mult:Mult15|mult_fus:auto_generated|le5a"    The part of the code where i try to use MUX (last 5 lines are under comment)  --========== Convolution Kernel Declaration ==========-- process(rst, kernel_sel) begin if(rst'event and rst = '0')then if(kernel_sel = '0')then kernel <= ( (X"00", X"00", X"00", X"00", X"00"), (X"00", X"01", X"00", X"ff", X"00"), (X"00", X"02", X"00", X"fe", X"00"), (X"00", X"01", X"00", X"ff", X"00"), (X"00", X"00", X"00", X"00", X"00") ); else kernel <= ( (X"01", X"02", X"00", X"fe", X"ff"), (X"04", X"08", X"00", X"f8", X"fc"), (X"06", X"0c", X"00", X"f4", X"fa"), (X"04", X"08", X"00", X"f8", X"fc"), (X"01", X"02", X"00", X"fe", X"ff") ); end if; end if; end process; -- kernel <= ( (X"01", X"02", X"00", X"fe", X"ff"), -- (X"04", X"08", X"00", X"f8", X"fc"), -- (X"06", X"0c", X"00", X"f4", X"fa"), -- (X"04", X"08", X"00", X"f8", X"fc"), -- (X"01", X"02", X"00", X"fe", X"ff") ); --====================================================--  Do someone have any idea what the reason to warning messages and how can i solve this problem....?  The whole code is attached (used as a "component" in the project)  Thanks in advance

[Altera_Forum]

but why use rst as clock in the mux?

[Altera_Forum]

--- Quote Start ---  but why use rst as clock in the mux?  --- Quote End ---    The reason for this came from VGA driver.  As i wrote, i tried to use MUX in all know ways (IF, CASE, WHEN, WITH SELECT) combined with clock and without clock, and every time i get the same warning messages  Without using MUX, everything is work just fine  I just want to understand, what are the reason/s to the warning messages and how i can solve this

[Altera_Forum]

--- Quote Start ---  The reason for this came from VGA driver.  As i wrote, i tried to use MUX in all know ways (IF, CASE, WHEN, WITH SELECT) combined with clock and without clock, and every time i get the same warning messages  Without using MUX, everything is work just fine  I just want to understand, what are the reason/s to the warning messages and how i can solve this  --- Quote End ---    Using rst as clock by itself does not explain the problem but you should not do that. What drives rst. I know it is input to the module. The quickest test is to remove that edge.

[Altera_Forum]

could it be your warnings are benign and your design does not work due to your setup. Do you get the mux synthesised?

[Altera_Forum]

How about posting more than just a code snippet. The code you posted bares no relation to the warnings, so I have no idea whats going on. There is nothing wrong with your code (apart from the odd way you're using reset as a clock) so I suspect the problem lies elsewhere.

[Altera_Forum]

The code in post# 1 doesn't compile due to index shift_reg row_length errors.

[Altera_Forum]

--- Quote Start ---  Using rst as clock by itself does not explain the problem but you should not do that. What drives rst. I know it is input to the module. The quickest test is to remove that edge.  --- Quote End ---    After removing the edge the project start working, thanks :)  But warning messages still appear.  Anyway, what may be the reason to the warning messages...?      --- Quote Start ---  The code in post# 1 doesn't compile due to index shift_reg row_length errors.  --- Quote End ---    Sorry, i forgot to change (for this post) generic values in entity of conv_2d_X.vhd, anyway in my project i do this by using "generic map" in top *.vhd file of the project.  I attached the correct vhdl files in post# 1, now it must compile.

[Altera_Forum]

--- Quote Start ---    Anyway, what may be the reason to the warning messages...?     --- Quote End ---    LCELL buffers can be used to stop the tool optimising logic cells away. That is unlike registers, the tool may otherwise remove logic using equivalent circuit. With registers it respects your code except things like duplication or removing duplicate registers or packing or retiming.  keeping your logic or not should not alter functionality though it changes delay but you are supposed to have a synchronous design that is tolerant to delay variations within timing limits of your design.  So in short it looks like your tool synthesis stage decides to insert LCELL buffers but fitter rejected that.