multiple clock problem

[Altera_Forum]

Hey! I am a beginner in VHDL programming and would like to ask a question to more advanced users. I am trying to write a simple shift register in order to control the stepper motor. Everything was ok to the moment, when I tried to add velocity control. I am using Altera DE1 board, where is internal 50 MHz clock, so my solution was to use four counters with different values of modulus and design shift register with four clock inputs (clock1, clock2, clock3, clock4). Of course in one moment only one clock is on, but quartus shows errors, which I have no idea how to solve:  

 1. can't infer register for y_act.d because its behavior depends on the edges of multiple distinct clocks 2. can't infer register for y_act.d because it does not hold its value outside the clock edge 3. couldn't implement registers for assignments on this clock edge   Here is a code and schematic in the attachment:  library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;   entity stepper is  port ( resetn , clock1, clock2, clock3, clock4, dir : in STD_LOGIC ;  phase : out STD_LOGIC_VECTOR (3 downto 0) );  END stepper;   architecture behavior of stepper is  type state_type is (A, B, C, D);  signal y_act , y_next : state_type ;       begin    process ( y_act )   begin   if ( dir = '1') then   case y_act is    when A => y_next <= B;    when B => y_next <= C;    when C => y_next <= D;    when D => y_next <= A;    when others => y_next <= A;      end case ;  else  case y_act is   when A => y_next <= D;    when B => y_next <= A;    when C => y_next <= B;    when D => y_next <= C;    when others => y_next <= A;      end case; end if;   end process ;       process ( clock1, clock2, clock3, clock4 )  begin     if (clock1'event and clock1 = '1' ) then  if ( resetn = '0') then -- synchronous clear  y_act <= A;  else  y_act <= y_next;  end if;   elsif (clock2'event and clock2 = '1' ) then  if ( resetn = '0') then -- synchronous clear  y_act <= A;  else  y_act <= y_next;  end if;   elsif (clock3'event and clock3 = '1' ) then  if ( resetn = '0') then -- synchronous clear  y_act <= A;  else  y_act <= y_next;  end if;   elsif (clock4'event and clock4 = '1' ) then  if ( resetn = '0') then -- synchronous clear  y_act <= A;  else  y_act <= y_next; end if;   end if;   case y_act is  when A => phase <= "0001";      when B => phase <= "0010";    when C => phase <= "0100";      when D => phase <= "1000";       when others => phase <= "1000";    end case ;   end process ;     end behavior ;     I will be very grateful for any help.

[Altera_Forum]

Just one thing: VHDL is description language, nothing similar to C. Take some book, learn basic concepts behind it. How do you think your process with 4 clocks will be implemented in hardware?

[Altera_Forum]

And what logic do you expect this to map to? The registers on FPGA only have a single clock, so 4 clocks are not allowed. And you can only use either rising or falling edge, not both. 

 WHat I think you want to do is generate clock enables and clock the design on the system clock.