Hi,I do not have any set up /hold violations in my design, but getting net delay timing violations in the range of 60 ps in two paths. I am fining it difficult to remove those violations. Please, Let me know if this can cause any potential issues if not fixed?
Is it a net delay inside the FIFO? I think that is overconstrained to 0.8 the period, where there is no reason for that to be done. (It could just by 1.0 * period).