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Valued Contributor III
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newbie in vhdl

good afternoon people. I'm a newbie in vhdl and i have problems about test bench. My area director has left me some problems. If anyone could help me with logs and the last two problems. 

 

the link is as follows 

 

http://users.ictp.it/~fpga/2006/exercises/lab-trieste2006-parta.pdf
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Valued Contributor III
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Re: newbie in vhdl

What exactly is the problem? Have you attempted the problems yourself?

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Valued Contributor III
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Re: newbie in vhdl

Probably some specific examples or error that you observed with test bench would be helpful for understanding your issue.

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Valued Contributor III
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Re: newbie in vhdl

one of my problems about test bench is the next: Design and Simulate a 12-Bit Magnitude Comparator using a cascade of three 74F85 

4-Bit Magnitude Comparators 

 

VHDL CODE (COMPILE GOOD) library ieee; use ieee.std_logic_1164.all; entity comparador_12 is port( num1 : in std_logic_vector(3 downto 0); num2 : in std_logic_vector(3 downto 0); menor : out std_logic; igual : out std_logic; mayor : out std_logic ); end comparador_12; architecture behavioral of comparador_12 is begin process(num1,num2) begin if (num1&num1&num1 > num2&num2&num2 ) then menor <= '0'; igual <= '0'; mayor <= '1'; elsif (num1&num1&num1 < num2&num2&num2) then menor <= '1'; igual <= '0'; mayor <= '0'; else menor <= '0'; igual <= '1'; mayor <= '0'; end if; end process; end behavioral;  

 

TEST BENCH library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparador_12_tb is end comparador_12_tb; architecture behavior of comparador_12_tb is --declaro mis señales de entrada signal num1,num2 : std_logic_vector(3 downto 0) :=(others => '0'); signal menor,igual,mayor : std_logic:='0'; begin --instancia de entidad UUT : work.comparador_12 port map(num1,num2,menor,igual,mayor); --definicion del estimulo de proceso tb : process begin num1&num1&num1<="100111000100"; --num1 = 2500 num2&num2&num2<="111011011000"; --num2 = 3800 wait for 10 ns; num1&num1&num1<="100110011001"; --num1 = 2457 num2&num2&num2<="010111100011"; --num2 = 1507 wait for 10 ns; num1&num1&num1<="111111111111"; --num1 = 4095 num2&num2&num2<="111111111111"; --num2 = 4095 wait for 10 ns; num1&num1&num1<="100010001000"; --num1 = 2184 num2&num2&num2<="001101110111"; --num2 = 887 wait; end process tb; end; 

 

when compile with tb i have 10 errores.  

The next is Error (10500): VHDL syntax error at comparador_12_tb.vhd(19) near text "&"; expecting "(", or "'", or "."
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Valued Contributor III
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Re: newbie in vhdl

Please post your code in code tags next time. 

You cannot use '&' to make a vector you assign to.  

Either split the bit pattern or use ',' instead of the ampersand. 

 

[edit]See this thread for things to watch out for if you are using the latter. 

http://www.alteraforum.com/forum/showthread.php?t=25484 

[/edit] 

(http://www.alteraforum.com/forum/showthread.php?t=25484)
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Valued Contributor III
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Re: newbie in vhdl

You cant do what you are trying to do. you're trying to assign the same signal with 3 different bit patterns.

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