output or inout port "outA" must be connected to a structural net expression

[CJT]

//block1

module block1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
	outA = inA;
	outB = outA;
	outC = outB;
end
endmodule

//block2

module block2 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
	outC = outB;
	outA = inA;
	outB = outA;
end
endmodule

//block 3

module block3 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
	outB = outA;
	outA = inA;
	outC = outB;
end
endmodule

Code the aboveDUT blocks using 3 different ordering:

module ordering1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;

block1 block1_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block2 block2_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));
block3 block3_inst (.clk(clk), .inA(inA), .outA(outA), .outB(outB), .outC(outC));

endmodule

Error (10663): Verilog HDL Port Connection error at ordering1.v(6): output or inout port "outA" must be connected to a structural net expression
Error (10663): Verilog HDL Port Connection error at ordering1.v(6): output or inout port "outB" must be connected to a structural net expression
Error (10663): Verilog HDL Port Connection error at ordering1.v(6): output or inout port "outC" must be connected to a structural net expression

How to solve the above error?

[IntelSupport]

Hi Chee,

The error message indicates that the output ports "outA", "outB", and "outC" of the "ordering1" module must be connected to a "structural net expression", which means that they must be connected to a wire or register signal. But, your current implementation, the "outA", "outB", and "outC" ports are connected directly to the corresponding output ports of the "block1_inst", "block2_inst", and "block3_inst" instances, which are register signals.

To fix this error, you should create new wire or register signals to connect to the "outA", "outB", and "outC" ports of the "ordering1" module. You can do this by declaring new wires or registers using the "wire" or "reg" keywords and connecting these signals to the "outA", "outB", and "outC" ports of the "ordering1" module.

Example:

module ordering1 (clk, inA, outA, outB, outC);

 input clk, inA;

 output reg outA, outB, outC; // changed from reg to wire or output

 wire block1_outA, block1_outB, block1_outC;

 wire block2_outA, block2_outB, block2_outC;

 wire block3_outA, block3_outB, block3_outC;

 block1 block1_inst (.clk(clk), .inA(inA), .outA(block1_outA), .outB(block1_outB), .outC(block1_outC));

 block2 block2_inst (.clk(clk), .inA(inA), .outA(block2_outA), .outB(block2_outB), .outC(block2_outC));

 block3 block3_inst (.clk(clk), .inA(inA), .outA(block3_outA), .outB(block3_outB), .outC(block3_outC));

 assign outA = block1_outA;

 assign outB = block2_outB;

 assign outC = block3_outC;

endmodule

This should resolve the issue.

p/s: If any answer from the community or Intel Support are helpful, please feel free mark and solution, give kudos and rate 5/5 survey.

[IntelSupport]

Hi Chee,

May I know if there is any update from previous reply

p/s: If any answer from the community or Intel Support are helpful, please feel free mark and solution, give kudos and rate 5/5 survey.

[IntelSupport]

 As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey