I have an existing Stratix5 design and want to check the parameter settings of PLLs and GTs. In Vivado, these are conveniently shown in the technology viewer, but I can't find a way to do this in Quartus. I'm also not finding these parameter details documented. I've looked in all the docs one would expect, V-Series Transceiver PHY IP Core User Guide, Quartus Handbooks (3 volumes), Stratix V Device Handbook: Transceivers).
For example, Xilinx documents in detail the various ways their transceivers can be configured (eg., clock mux'ing through PMA/CDR). Each parameter down to the individual bit is documented, and, each can be correlated and viewed in the technology.
Am I missing something, or does Altera really not provide this level of detail?
Thanks,
Mike
