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Altera_Forum
Honored Contributor I
756 Views

efficient global memory access for dynamic indexing

Hello, 

my OpenCL task (no ND-range) has a dynamic indexing access inside a loop.  

what is the maximum expected bandwidth to get from this code for 'value' array ? will coalescence access work for it? 

all arrays are very huge size global variables. 

actually what I get currently is 1 32-bit data (float) per 2 clock cycles which I guess is sub-optimum. 

 

for (unsigned i = 0; i < n; i++) 

acc = 0.0; 

ei = end_index

si = start_index

for(unsigned j = si; j < ei; j++) 

acc += value[dyn_index[j]]; 

next_value[i] = acc; 

}
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1 Reply
Altera_Forum
Honored Contributor I
17 Views

I explained the math behind the memory bandwidth utilization in the other thread: 

 

http://www.alteraforum.com/forum/showthread.php?t=58222 

 

(And previously here: http://www.alteraforum.com/forum/showthread.php?t=57099&p=232613

 

For such kernels I would recommend an NDRange implementation since instead of a fixed II, you will get a runtime scheduler which will try to minimize the bubbles and the stalls in the pipeline by varying the II at runtime. Furthermore, you can easily replicate your module using num_compute_units which could provide some benefit for such a kernel. However, as I explained in the other thread, random access will result in very poor memory performance regardless of what you do, and pretty much the only thing that can help is an efficient and complex memory controller and a sophisticated cache hierarchy, none of which exists on current-generation FPGAs.