please help me about avering of array at 1 clc pulse

[Altera_Forum]

hello,  

I'm trying to making avering filter.First &#305; create a matrix which is 4*4.And I covered this vith zeros to protect size of matrix. and after that I make filtering process. then I save the values in a new matrix which is name is matris_out. but when I compile the code I get a problem like : Error: Design requires 1153 I/O resources -- too many to fit in 400 available in the selected device or any device in the device family. how can &#305; solve this. I add my code and I need your help because I'm new at VHDL.  LIBRARY ieee; USE ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE work.my_data_types.all;      ENTITY projemm IS    GENERIC (n : INTEGER := 4);     PORT( clk : IN STD_LOGIC;  --matris_in : IN integer_array(0 TO n+1);  matris_out : OUT integer_array       ); end projemm;   architecture main of projemm is     SIGNAL matris_in :integer_array :=((0,0,0,0,0,0), (0,25,69,54,30,0), (0,215,14,3,98,0), (0,51,150,117,200,0), (0,100,13,82,9,0), (0,0,0,0,0,0));   --SIGNAL matris_out :int_arr_out :=((0,0,0,0), (0,0,0,0), (0,0,0,0), (0,0,0,0) );   begin   PROCESS(clk)   BEGIN   IF(clk'EVENT AND clk='1') THEN FOR i IN 1 TO n LOOP   FOR j IN 1 TO n LOOP  matris_out(i-1,j-1) <= (1 / 9) * (matris_in(i-1,j-1) + matris_in(i-1,j) + matris_in(i-1,j+1) + matris_in(i,j-1) + matris_in(i,j) + matris_in(i,j+1) + matris_in(i+1,j-1) + matris_in(i+1,j) + matris_in(i,j+1));      end LOOP;   end LOOP;   END IF;   end PROCESS;       end main;

[Altera_Forum]

You're trying to compile the design directly into a chip - it doesnt have enough pins to fit each bit of each value to a separate pin. Remember integers are 32 bits. 

I assume/hope you are intending this to be a block as part of a larger design. 1153 IOs is about what the top end stratix devices have, and you wouldnt normally assign them all to something like this.  what you can do for now is assign all pins as virtual - this allows you to see how big the design will be without assigning actual pins. But you cannot run the chip with virtual pins.

[Altera_Forum]

Actually I try to make division of this according the clk pulse.I think if I change this part  

 IF(clk'EVENT AND clk='1') THEN FOR i IN 1 TO n LOOP  FOR j IN 1 TO n LOOP matris_out(i-1,j-1) <= (1 / 9) * (matris_in(i-1,j-1) + matris_in(i-1,j) + matris_in(i-1,j+1) + matris_in(i,j-1) + matris_in(i,j) + matris_in(i,j+1) + matris_in(i+1,j-1) + matris_in(i+1,j) + matris_in(i,j+1));  I can solve the problem.but &#305; coudn't understand how can I make smaller pieces according the clk.Actually I must get a bigger matrix for real project.Could you clarify your answer?thanks

[Altera_Forum]

You cannot directly map the matrix to pins - there just arnt enough pins. You will probably have to store the matrix in a memory.

[Altera_Forum]

Hello, 

 I want to ask sth. I don't have any error while compilation and simulation. But there is no change at output values. The values aren't assigned. How I solve this problem?  Thanks

[Altera_Forum]

you question doesnt make any sense. Can you post some code with specific problems?

[Altera_Forum]

--- Quote Start ---  you question doesnt make any sense. Can you post some code with specific problems?  --- Quote End ---     I can send my code but there is no error while compilation and simulation.So I can send all my code to be clear.  I couldn't see output values on simulation report. I couldn't understand.   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all;--cevirmeler yapabilecegim icin kullanmak zorundayim. use ieee.std_logic_unsigned.all;--std_logic_vector operasyonlarina izin verir.--std_logic_vector'e aritm. islemler uygulamayi saglar USE work.my_data_types.all;--package'i dahil etmek icin kullandim. --use ieee.std_logic_arith;--conv. islemler icin use ieee.numeric_std;       ENTITY projem2 IS    GENERIC (    n : INTEGER := 4    );       PORT( clk : IN STD_LOGIC;  we : in std_logic;  --matris_in : IN integer_array;  finish : OUT bit;  --deneme : OUT bit;  matris_out : out int_arr_out       );           end projem2;   architecture behv of projem2 is    SIGNAL matris_in :integer_array :=((0,0,0,0,0,0), (0,25,69,54,30,0), (0,215,14,3,98,0), (0,51,150,117,200,0), (0,100,13,82,9,0), (0,0,0,0,0,0));  SIGNAL s1,s2,s3,s4,s5,s6,s7,summary : unsigned(7 downto 0); SIGNAL counter : INTEGER;   --SIGNAL matris_out :int_arr_out;       SIGNAL tmp3: integer; SIGNAL tmp2: unsigned(7 downto 0); SIGNAL tmp4: unsigned(7 downto 0); SIGNAL tmp5: unsigned(7 downto 0); TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8); SIGNAL pr_state,nx_state: state;   --bir haf&#305;za alan&#305; olusturulmali...büyük bir matris için kullanilirken.   --type ram_t is array( 0 to 15) of std_logic_vector( 15 downto 0); --variable rama : ram_t;   function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is variable a1 : unsigned(a'length-1 downto 0):=a; variable b1 : unsigned(b'length-1 downto 0):=b; variable p1 : unsigned(b'length downto 0):= (others => '0'); variable i : integer:=0;   begin for i in 0 to b'length-1 loop p1(b'length-1 downto 1) := p1(b'length-2 downto 0); p1(0) := a1(a'length-1); a1(a'length-1 downto 1) := a1(a'length-2 downto 0); p1 := p1-b1; if(p1(b'length-1) ='1') then a1(0) :='0'; p1 := p1+b1; else a1(0) :='1'; end if; end loop; return a1;   end divide;         signal a : unsigned(7 downto 0) ; signal b : unsigned(7 downto 0) ; signal c : unsigned(7 downto 0) :=(others => '0');           function adder (A,B : in integer) return unsigned is --integer degerler 8 bit olcagi icin (7 DOWNTO 0)kulland&#305;m.    variable tmp : unsigned(7 downto 0);  variable SUM : unsigned(7 downto 0);    begin    tmp := conv_unsigned(A,8) + conv_unsigned(B,8) ;  Sum := tmp(7 DOWNTO 0);  --SUM:=tmp2 (7 DOWNTO 0);      return SUM; -- return olan deger std_logic_vector tipinde!!!    end adder;        BEGIN          PROCESS(clk,we)        BEGIN          if(we='1') then  pr_state <=st0;    elsif(clk'event and clk = '1') then    pr_state <= nx_state;    end if;  END PROCESS;    PROCESS(pr_state,counter)    BEGIN  counter <= 0;    --deneme1<='1';    FOR i IN 1 TO n LOOP  FOR j IN 1 TO n LOOP    counter <= 1;    CASE pr_state IS  WHEN st0 =>    IF(counter = 1) THEN    s1<=adder(matris_in(i-1,j-1),matris_in(i-1,j));  --deneme2<='1';    counter<=counter + 1;  nx_state <= st1;        end if;    WHEN st1 =>    IF(counter = 2) then    s2<=adder(conv_integer(s1),matris_in(i-1,j+1));      counter<=counter + 1;  nx_state <= st2;        end if;    WHEN st2 =>    IF(counter = 3) THEN    s3<=adder(conv_integer(s2),matris_in(i,j-1));      counter<=counter + 1;  nx_state <= st3;    --deneme3<=counter;    end if;    WHEN st3 =>    IF(counter = 4) THEN       s4<=adder(conv_integer(s3),matris_in(i,j));      counter<=counter + 1;  nx_state <= st4;    end if;          WHEN st4 =>    IF(counter = 5) THEN       s5<=adder(conv_integer(s4),matris_in(i,j+1));    counter<=counter + 1;  nx_state <= st5;    end if;        WHEN st5 =>    IF(counter = 6) THEN      s6<=adder(conv_integer(s5),matris_in(i+1,j-1));    counter<=counter + 1;  nx_state <= st6;    end if;      WHEN st6 =>     IF(counter = 7) THEN    s7<=adder(conv_integer(s6),matris_in(i+1,j));    counter<=counter + 1;  nx_state <= st7;    end if;      WHEN st7 =>    IF(counter = 8) THEN    summary<=adder(conv_integer(s7),matris_in(i+1,j+1));    counter<=counter + 1;  nx_state <= st8;    end if;          WHEN st8 =>    IF(counter = 9) THEN      tmp4<=conv_unsigned(9,8);  tmp5<=conv_unsigned(1,8);    c <= divide ( tmp5 , tmp4 );    tmp3<=(conv_integer(summary)* conv_integer(c));  tmp2<=conv_unsigned(tmp3,8);    matris_out(i-1,j-1)<=conv_integer(tmp2);  --counter<=counter+1; --???        --finish<='1' WHEN (i =n AND j = n) ELSE '0';      --deneme<=tmp2; -- yeni degeri ekranda gormek icin            end if;      if (i= n AND j=n ) THEN      finish<='1';      end if;    END CASE;      end loop;  end loop;  end process;      end behv;  At this code I try to make average filter on a matrix(matris_in which is 6*6 matrix).matris_out is a output matrix(4*4). Values which are averaged of matris_in,is saved at matris_out.  matris_in is6*6.Because I apply zero padding to a 4*4 matrix.

[Altera_Forum]

wheres the testbench code?

[Altera_Forum]

--- Quote Start ---  wheres the testbench code?  --- Quote End ---    I create only two .vhd files. I sent the first one. and this is the second one. I got it wrong?   LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;--std_logic_vector operasyonlarina izin verir.--std_logic_vector'e aritm. islemler uygulamayi saglar use ieee.std_logic_unsigned; --use ieee.numeric_std.all;     PACKAGE my_data_types IS     TYPE integer_array IS ARRAY(0 TO 5,0 TO 5) OF integer range 0 to 255; TYPE int_arr_out IS ARRAY (0 TO 3,0 TO 3) OF integer range 0 to 255;   END my_data_types;