i want to generate a bus clock by pll.
for example, inclk is 40Mhz, pllout is 100Mhz.
the pllout was used as the clock of bus interface.
inclk was used by internal logic.
i don't want to treat pllout and inclk as two asynchronous clock, and they are not, i think.
but the mode of altpll can't be chosen.
in normal mode, quartus would aligned the pllout at register port, which would lead to hold violation.
zero buffer delay and source synchronous seems not suitable.
what i wanted is to align pllout and inclk at two time domain's crossing.
which mode is the best?
