post-synthesis simulation of a quartus design in modelsim

Altera_Forum · ‎09-30-2007

hey all.

i am trying use modelsim altera to perform post-synthesis simulation of my design synthesized in quartus II. These are the steps i am doing:

i) perform analysis&synthesis of my design in quartus

ii) complie the testbench(which i have written), the .vo file(generated during analysis&synthesis), and the cycloneii_atoms.v file(which is provided in the libraries) in modelsim. (i am using cyclone II device family)

iii) start simulation & selecting the testbench module for simulation.

the error comes while loading the cycloneii.v

this verilog file contains a number of modules. the error is for one of the modules and it is like this(within 'quote&unquote'):

quoting the error:

# ** Error: (vsim-3389) D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/simulation/modelsim/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (1st connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

unquoting it.

(TO EXPLAIN - testbench_MOD is the top level module in my testbench, and the testbench is testing the working of my loop_accelerator design. the "outreg_D_mux is in cycloneii.v, and is an instantiation of a mux module in cycloneii.v)

infact there are 7 such errors, and in the end it says the following &stops:

# ** Fatal: (vsim-3365) D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/simulation/modelsim/cycloneii_atoms.v(5764): Too many port connections. Expected 4, found 11.

can anyone help me understand what is going on exactly?

thanks,

-anu

Altera_Forum · ‎10-01-2007

You don't need to compile cycloneii_atoms.v if you're using Modelsim-Altera. It has already been pre-compiled. You just need to specify the pre-compiled library using the -L switch

Example:

vsim -t 1ps -L cycloneii_ver -L work my_tb

cycloneii_ver is the pre-compiled library for cycloneii_atoms.v

Also, FYI in case you're not aware that the VO file is not generated by default if you just run Analysis & Synthesis. It is only generated by default during full compilation. You required to run it manually in different flow. You can refer to "Generating a Post-Synthesis Simulation Netlist" in the Modelsim Handbook.

Hope it helps.

Altera_Forum · ‎10-01-2007

hey...thanks!

but i am still getting the same error.

Altera_Forum · ‎10-01-2007

How is your simulation script looks like?

Altera_Forum · ‎10-01-2007

it looks like this:

transcript on

if {[file exists gate_work]} {

vdel -lib gate_work -all

}

vlib gate_work

vmap work gate_work

vlog -vlog01compat -work work +incdir+. {loopaccelerator.vo}

vlog -vlog01compat -work work +incdir+D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/synth_result {D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/synth_result/testbench_mod.v}

vsim -t 1ps -L cycloneii_ver -L gate_work -L work testbench_MOD

add wave *

view structure

view signals

run -all

Altera_Forum · ‎10-01-2007

just for completeness, i am giving the whole list of commands( shown within modelsim) when i start simulation from within quartusII (via EDA Simulation Tool --> Run Gate level Simulation ):

Reading C:/altera/71sp1/modelsim_ae/tcl/vsim/pref.tcl

# do loopaccelerator_run_msim_gate_verilog.do

# if {[file exists gate_work]} {

# vdel -lib gate_work -all

# }

# vlib gate_work

# vmap work gate_work

# Copying C:\altera\71sp1\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini

# Modifying modelsim.ini

# ** Warning: Copied C:\altera\71sp1\modelsim_ae\win32aloem/../modelsim.ini to modelsim.ini.

# Updated modelsim.ini.

#

# vlog -vlog01compat -work work +incdir+. {loopaccelerator.vo}

# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006

# -- Compiling module LoopAccelerator

#

# Top level modules:

# LoopAccelerator

#

# vlog -vlog01compat -work work +incdir+D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/synth_result {D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/synth_result/testbench_mod.v}

# Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006

# -- Compiling module testbench_MOD

#

# Top level modules:

# testbench_MOD

#

# vsim -t 1ps -L cycloneii_ver -L gate_work -L work testbench_MOD

# vsim -L cycloneii_ver -L gate_work -L work -t 1ps testbench_MOD

# // ModelSim ALTERA 6.1g Aug 12 2006

# //

# // THIS WORK CONTAINS TRADE SECRET AND

# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY

# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS

# // AND IS SUBJECT TO LICENSE TERMS.

# //

# Loading gate_work.testbench_MOD

# Loading gate_work.LoopAccelerator

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_lcell_ff

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_lcell_comb

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_io

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_mux21

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_dffe

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_asynch_io

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_clkctrl

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_mux41

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_ena_reg

# ** Error: (vsim-3043) D:/AnuChaudhary/Study/Project/Quartus/24Septonwards/loopacc/synth_result/testbench_mod.v(56): Unresolved reference to '_processor_0_done' in loop_accelerator._processor_0_done.

# Region: /testbench_MOD

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.CYCLONEII_PRIM_DFFE

# ** Warning: (vsim-3620) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(104): Specify path destination port 'Q' has no drivers on it.

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/input_reg

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (1st connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (2nd connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (3rd connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (4th connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (5th connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (6th connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Error: (vsim-3389) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Port '(null)' not found in the connected module (7th connection).

# Region: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux

# ** Fatal: (vsim-3365) C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v(5764): Too many port connections. Expected 4, found 11.

# Time: 0 ps Iteration: 0 Instance: /testbench_MOD/loop_accelerator/\CLK~I\/outreg_D_mux File: C:/altera/71sp1/modelsim_ae/win32aloem/../altera/verilog/src/cycloneii_atoms.v

# FATAL ERROR while loading design

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./loopaccelerator_run_msim_gate_verilog.do PAUSED at line 12

Altera_Forum · ‎10-01-2007

"loopaccelerator_run_msim_gate_verilog.do" is the simulation script file I have pasted in the message before the last one.

in this file, line 12 corresponds to this line:

vsim -t 1ps -L cycloneii_ver -L gate_work -L work testbench_MOD

Altera_Forum · ‎10-04-2007

Looking at the error's, it leads me to believe that there may be a problem with your testbench? What you can do is load your *.vo file independent of your testbench. If you can load the *.vo file then this would probably rule out the possibility that there is a problem with the Q II netlist generation of the *.vo and any problems relating to the cycloneii library.

Here's the command to load the .vo:

vsim -L cycloneii_ver -L gate_work -L work loopaccelerator (I'd run Modelsim-Altera independent of the Quartus II software to test this case).

Additionally, were you able to perform a RTL (functional) simulation without using NativeLink to invoke the ModelSim-Altera simulator?

Try the above and post your results... Good luck!

--pld_wiz

Altera_Forum · ‎10-05-2007

thanks pld_wiz! here are the results:

1. when i try doing "vsim -L cycloneii_ver -L gate_work -L work work.LoopAccelerator", everything loads fine.

# vsim -L cycloneii_ver -L gate_work -L work work.LoopAccelerator

# Loading work.LoopAccelerator

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_lcell_ff

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_lcell_comb

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_io

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_mux21

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_dffe

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_asynch_io

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_clkctrl

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_mux41

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.cycloneii_ena_reg

# Loading C:\altera\71sp1\modelsim_ae\win32aloem/../altera/verilog/cycloneii.CYCLONEII_PRIM_DFFE

2. when i perform RTL simulation 'with' using Native link to invoke modelsim altera, my testbench works correctly & this is a part of what i get in the response window of modelsim:

-- Compiling module testbench_MOD

#

# Top level modules:

# testbench_MOD

#

# vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cycloneii_ver -L rtl_work -L work testbench_MOD

# vsim -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cycloneii_ver -L rtl_work -L work -t 1ps testbench_MOD

# // ModelSim ALTERA 6.1g Aug 12 2006

# //

# // THIS WORK CONTAINS TRADE SECRET AND

# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY

# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS

# // AND IS SUBJECT TO LICENSE TERMS.

# //

# Loading rtl_work.testbench_MOD.......(loads other files&finishes correctly)

>>>>>> so here, the vsim command has a number of libraries included (lpm_ver, altera_ver...etc)

3. if i perform a rtl simulation 'without' using Native link to invoke modelsim altera, everything is running fine

Just to make sure that i am doing the rtl simulation directly thru modelsim correctly, these are the steps i am taking :

>i creat a new project

> add my testbench.v and other verilog design files to this project (i do not add loopaccelerator.vo)

> then i simulate using "vsim work.testbench_MOD"

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.

do u see some relation now?

Altera_Forum · ‎10-08-2007

Hi Anu,

For Cyclone II gate-level simulation, all you need to do in Modelsim-Altera software to specify the Cyclone II library is as follows: "-L cycloneii_ver". For gate-level simulation, this is the only library that is required.

Since you were able to load the *.vo by itself, I believe that there is a mis-match between the testbench and the *.vo netlist generated by the Q II software. You may want to double check the port map of the .vo against the testbench.

You may want to try using the latest version of the Q II software ver 7.2 and Modelsim-Altera 6.1g (for Q II 7.2) to see if the problem still exist?

If 7.2 generates the same errors, then I'd inquire with the Altera Technical Support staff to see if they can help you find a resolution.

Good luck and please post what you find... it'll be helpful for me in case i should run into this in the future!!

pld-wiz

Altera_Forum · ‎10-10-2007

figured out what the problem was....i was sampling one of the internal wires in my testbench. since it was not a port so was not visible outside the module. therefore the mismatch during post-syn simulation.

thanks for all the pointers!

-anu

Altera_Forum · ‎10-10-2007

Anu,

I'm glad you were able to resolve the issue!

-pld_wiz