Verilog error. Supposedly can't find pin, but it's there

Altera_Forum · ‎10-13-2007

Hi, I'm using the Max+Plus II suite to develop a Verilog project. I have an annoying problem, which I have reduced to the following toy example.

I have one file mini.v (which compiles flawlessly) containing the following.

module mini( data, clock, exit);
input data, clock;
output exit;
reg  exit;
always @ (posedge clock) begin
	if (data == 0) exit= 2'b11;
end
	
endmodule

I also have this file maxi.v.


module maxi( A, B, rlj, C);
input A, B, rlj;
output C;
reg  C;
mini M1 (.data(A), .clock(rlj), .exit(C) );
endmodule

When I try to compile this, it gives the following error.

error: can't find a pin in the design file that corresponds to pinstub/port 'exit' in the symbol, function prototype, or other construct 'm1' that represents the file.

I can't understand why is there a problem, since I'm passing the M1 instance 'C' as a pin for 'exit'.

Thanks in advance for any comment you might provide.

Altera_Forum · ‎10-15-2007

Probably because your maxi module doesn't declare the C output correctly, should be:

module maxi( A, B, rlj, C);

input A, B, rlj;

output [1:0] C;

wire [1:0] C;

Altera_Forum · ‎10-15-2007

Thanks a lot!!

I changed both instances of "output ..." to "output [1:0]" and now it works! thanks a lot again