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Hi,
In my sdc file I calculate various timing values based on a constant that I set in the file. For example:# Clock frequency in MHz
set clk_base_freq 14.0
# Clock period in ns
set clk_base_period
create_clock -period $clk_base_period
When I use the above code, I get truncation warnings like this: --- Quote Start --- Time value "71.4285714286 ns" truncated to "71.428 ns" --- Quote End --- I could put rounding/truncation code, such as the following, into every expression, but that's a bit painful.
set clk_base_period
A better solution would be some sort of function, like this:
proc rndto {value places} {
set retval
return $retval
}
set clk_base_period
Unfortunately, this doesn't seem to work, or I can't find the appropriate syntax. What's the best solution to allowing calculations such as these, while avoiding the time value truncated messages? thanks, galen
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This seems rather extreme. Most people just specify their clock_base_period manually, rather than using a formula from the clock frequency. This avoids all of the truncation warnings.
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As I mentioned, this was just one example. This particular design uses a TI high-speed ADC, so I've adapted rysc's source synchronous example for the ADS4149 to my design.
# trace length in inches
set BD_adc_data_len_min 0.720
set BD_adc_data_len_max 0.830
set BD_adc_clock_len 1.070
# propagation delay for outer trace in ns/inch
set BD_prop 0.140
# propagation delay of traces in ns
set BD_adc_data_min
set BD_adc_data_max
set BD_adc_clock
# ################## ADS4122 -> FPGA Interface# ###################
# Create virtual clock for ADS4122. Phase-shift it -90 degrees to say
# it is center-aligned
create_generated_clock -source -phase -90 -name clk_adc_in
# The device does not spec what it is actually doing, but what it can
# provide. We will use our relationship to figure out what the
# ADS4122 is actually doing We will need to know the setup
# relationship and hold relationship to perform this calculation,
# which are just +90 degrees and -90 degrees in Explicit Clock Shift
# Mode
set relationship
# TI ADS4122 datasheet says it can provide a Tsu and Th to the FPGA:
set adc_tsu 2.3
set adc_th 0.35
# Need to calculate whave ADS4122 is actually doing
set adc_skew_max
set adc_skew_min
# The board skew need to be accounted for. Positive means data is
# longer than clk, negative means it is shorter than clk.
set board_data2clk_skew_max
set board_data2clk_skew_min
# Now just add the ADC skew and board skew to calculate external delays:
set adc_data_max
# set adc_data_max
set adc_data_min
# set adc_data_min
set_input_delay -clock clk_adc_in -max $adc_data_max }]
set_input_delay -clock clk_adc_in -min $adc_data_min }]
set_input_delay -clock clk_adc_in -max $adc_data_max }] -clock_fall -add_delay
set_input_delay -clock clk_adc_in -min $adc_data_min }] -clock_fall -add_delay
As you can see, there are many calculations here. It would be unwieldy to hard code all the values. Additionally, it's easy to imagine a more sophisticated setup where board trace lengths or other values are brought in automatically from other tools. Anyway, I'm surprised there isn't an easy way to eliminate these truncation messages.
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