preserving module hierarchy in .vo files

[Altera_Forum]

Hi, 

 I would like to use synthesized (.vo file) output in an existing ncverilog based testbench. The problem that I am running into is that some of the testbench rtl directly references signals using "top.entity.entity.signal". I am attempting to preserve the signals using the synthesis keep and synthesis preserve directives. I am also trying to preserve the module hierarchy using this tcl command:  set_instance_assignment -name EDA_FV_HIERARCHY BLACKBOX -to | -entity SPCTREG   Unfortunately, I still get this error:   ncelab: *E,CUVHNF (./TB_SP_MEM.v,348|21): Hierarchical name component lookup failed at 'TB_SP.SP.SPCTREG'   Any ideas ?   Thanks

[Altera_Forum]

--- Quote Start ---  Hi,   I would like to use synthesized (.vo file) output in an existing ncverilog based testbench. The problem that I am running into is that some of the testbench rtl directly references signals using "top.entity.entity.signal". I am attempting to preserve the signals using the synthesis keep and synthesis preserve directives. I am also trying to preserve the module hierarchy using this tcl command:  set_instance_assignment -name EDA_FV_HIERARCHY BLACKBOX -to | -entity SPCTREG   Unfortunately, I still get this error:   ncelab: *E,CUVHNF (./TB_SP_MEM.v,348|21): Hierarchical name component lookup failed at 'TB_SP.SP.SPCTREG'   Any ideas ?   Thanks  --- Quote End ---    Hi,  I would use "synthesis noprune" for preserving the signal. For preserving the hierachy I would try to define the enity as design partition. This should prevent flatten the design.  Kind regards  GPK