problem VHDL help in code please

[Altera_Forum]

problem solved thank you all

[Altera_Forum]

What exactly is the problem? Have you even made a start?

[Altera_Forum]

Hey Tricky  

Actually I am new to VHDL and I don't know where to start from. I would really appreciate your help  the started code    library ieee; use ieee.std_logic_114.all; entity MAC is port( rst, clk: in std_logic; A, B : in integer range 0 to 2**8-1; M : in integer range 0 to 2**1-1; s : out std_logic); end entity MAC -------------------------------------------------- architecture rtl of MAC is begin mycore: process(rst,clk) begin if rst = '1' then --- what to do---- else if rising_edge(clk) then ---------what to write ---------- else --------------- end process; end architecture rtl;

[Altera_Forum]

I would start with a VHDL tutorial, or a good textbook. We're not going to do the work for you. When you're stuck you can come back here with specific problems?

[Altera_Forum]

dear tricky  

I need to learn and I need this resources I really want to solve this and to learn as well so can you help me and please also don't close this thread I well put some code later to solve some errors   can you give me some pdfs or some videos to learn ? thank you

[Altera_Forum]

Altera provide a free online VHDL training course: 

 http://www.altera.co.uk/education/training/courses/ohdl1110

[Altera_Forum]

I agree with Tricky that doing the exercise from a scratch is not recommended Forum practice. 

 as a general guide I will suggest this:   your A input goes to a box(possibly register)then to mux then to mult then to register then mux then adder with feedback.    1) Name nodes: A, A_reg, mult_result, mult_reseult_reg, accum_result ...(you may not need naming all)   2) Every mux is equivalent to a conditional statement be it sequential or combinatorial   3) For mult you may just use operator *   4) For add use operator +   5) For any register you may instantiate it but since you are after rtl description then any assignment to a signal inside clock edge puts a register at assignment result    6) You will need to truncate the result (s) back to 8 bits

[Altera_Forum]

tomorrow I will put the code may you check it and correct it ???

[Altera_Forum]

--- Quote Start ---  tomorrow I will put the code may you check it and correct it ???  --- Quote End ---    plenty of correct code but see my notes below:   library ieee; use ieee.std_logic_114.all; ***************** typing error, should be use ieee.std_logic_1164.all; ***************** entity MAC is port( rst, clk: in std_logic; A, B : in integer range 0 to 2**8-1; M : in std_logic; s : out integer range 0 to 2**8-1); end entity MAC; *************** ok but I prefer this below for readability: entity MAC is port( rst : in std_logic; clk : in std_logic; M : in std_logic; A : in integer range 0 to 2**8-1; B : in integer range 0 to 2**8-1; s : out integer range 0 to 2**8-1 ); end entity; *************** -------------------------------------------------- -- no need to repeat library statements --library ieee; --use ieee.std_logic_114.all; architecture rtl of MAC is signal A_reg: integer range 0 to 2**8-1; signal B_reg: integer range 0 to 2**8-1; signal AB: integer range 0 to 2**8-1; signal old_S: integer range 0 to 2**8-1; signal AB_reg: integer range 0 to 2**8-1; signal old_S_reg: integer range 0 to 2**8-1; begin mycore: process(rst,clk) begin if rst = '1' then s <= '0'; -- ***** but s is integer? elsif rising_edge(clk) then if M = '1' then A_reg <= 0 ; B_reg <= 0; AB_reg <= 0; old_S_reg <= 0; else A_reg <= A; B_reg <= B; AB_reg <= AB; -- you don't need this extra register old_s_reg <= old_s; -- you don't need this extra register end if; AB <= A_reg + B_reg ; -- wrong, you have added before multiplication old_s <= old_s_reg * AB_reg; -- wrong, should multiply A_reg * B_reg then accumulate result s <= old_s; end if; end process; end architecture rtl;

[Altera_Forum]

and now ? can you help more about s as integer

[Altera_Forum]

kaz can I have your email

[Altera_Forum]

--- Quote Start ---  library ieee; use ieee.std_logic_1164.all; entity MAC is port( rst : in std_logic; clk : in std_logic; M : in std_logic; A : in integer range 0 to 2**8-1; B : in integer range 0 to 2**8-1; s : out integer range 0 to 2**8-1 ); end entity MAC; -------------------------------------------------- architecture rtl of MAC is signal A_reg: integer range 0 to 2**8-1; signal B_reg: integer range 0 to 2**8-1; signal AB: integer range 0 to 2**8-1; signal old_S: integer range 0 to 2**8-1; begin mycore: process(rst,clk) begin if rst = '1' then s <= '0'; -- ***** but s is integer? don't know what to do elsif rising_edge(clk) then if M = '1' then A_reg <= 0 ; B_reg <= 0; AB_reg <= 0; old_S <= 0; else A_reg <= A; B_reg <= B; end if; AB <= A_reg * B_reg ; old_s <= old_s_reg + AB_reg; s <= old_s; end if; end process; end architecture rtl;  and know ? can you help more  --- Quote End ---      really impressive for a beginner.It looks ok to me. 1) you need to assign 0 and not '0' to S at reset. Moreover you better reset all nodes inside process like S otherwise you get latches. 2) you can insert the * and + assignments inside the mux else...as well but it should do 3) your last challenge is to truncate final result into S within the range 0f 8 bits. your current code means S may overflow as it will accumulate several values of A*B. I am sure you can do that. The easiest way is to convert it to std_logic_vector and chop off some bits and convert it back to integer. It will be an exercise of type conversion experience.

[Altera_Forum]

--- Quote Start ---  kaz can I have your email  --- Quote End ---    you can send via private message at top left of menu. notice also that you have syntax error at signal name of old_s_reg(should be old_s)

[Altera_Forum]

I have to post more 4 reply in order to send a message :P  

  really do you think that code will work :D I am so happy to hear that   the problem of overflow : in the question s is integer of 8 bit changing the type will change the question is it right and in order to do that I need more tutorials   + thank you so mush and yes I am really a beginner in VHDL who have to solve more problems latter also

[Altera_Forum]

--- Quote Start ---  I have to post more 4 reply in order to send a message :P    really do you think that code will work :D I am so happy to hear that   the problem of overflow : in the question s is integer of 8 bit changing the type will change the question is it right and in order to do that I need more tutorials   + thank you so mush and yes I am really a beginner in VHDL how have to solve more problems latter also  --- Quote End ---    It should work, yes but obviously you need to simulate it first before going to hardware.  overflow issue: keep your code as it is. but name S as S_int then add a conversion assignment of integer S_int to S2 as std_logic_vector say of 20 bits (in fact depends how many samples you accumulate). If you expect to accumulate 16 samples then S2 will require 8+8+4 bits = 20 finally discard 12 LSBs from S2 and convert to integer S for output. or may want to discard MSBs(depends on your spec)

[Altera_Forum]

how to convert this vhdl code to verilog,please help me... 

signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80");

[Altera_Forum]

please delete this thread and thank you

[Altera_Forum]

--- Quote Start ---  please delete this thread and thank you  --- Quote End ---    The thread will not be deleted, it will remain in case others are in need of similar help.

[Altera_Forum]

--- Quote Start ---  how to convert this vhdl code to verilog,please help me... signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80");  --- Quote End ---    I suggest you start your own thread rather than trying to hijack someone else's