Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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problem in signaltap

Altera_Forum
Honored Contributor II
‎01-02-2013 04:40 PM
1,646 Views

Hello friends, 

 

I'm a newbe in signaltap tool in Quartus II. I can configure the signaltap to see input/output pins changes. 

But when I want to see the changes of registers of my design, it just shows '0' value without change and also one warning is added to the critical warnings: 

 

Critical Warning: Partially connected in-system debug instance "auto_signaltap_0" to 1 of its 27 required data inputs, trigger inputs, acquisition clocks, and dynamic pins. There were 0 illegal, 0 inaccessible, and 26 missing sources or connections. 

 

would you please help me? 

 

Thanks in advance.
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Altera_Forum
Honored Contributor II
‎01-02-2013 08:23 PM
720 Views

hi there, 

seems like the register you intended to monitor in SignalTap has been optimized "away" by the compiler (in fact the register is not really missing, but not referenced to by the name you think it is...). Thus the signal content cannot be shown in SignalTap. Nevertheless this is just (my) good guess based on the information given.  

To be sure the best would be to archive the Project and add it to the thread to check this...
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