Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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stopwatch clock code error

Altera_Forum
Honored Contributor II
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hii 

 

i am facing errors in generating vhdl code for stopwatch in Quartus2 12.1 version. 

 

please check the attached file and guide me. 

 

i want that file to be implemented on altera de1 board. 

 

regards.
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Altera_Forum
Honored Contributor II
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Hi, 

I copied the text in a new Textfile (VHDL) and ran a compilation.. Just getting some warnings as I did not defined a device / Pinout /... but no error... 

Which is the exact error you are facing? 

(I assume the filename is arg.vhd as you named the entitiy contained as arg. In case your file is saved as stopwatch.vhd, you have to Change arg to stopwatch in lines 5 and 36..) 

 

HTH
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