problem with Clock Constraint 3 bit modulo 5 counter

Altera_Forum · ‎04-22-2013

Dear Guru,

You may refer to the link as I posted the same question before at:

Forum > Coding Questions > Verilog and System Verilog > simple Infinite loop expansion header using Altera DE2-70 Cyclon ii

I am using Altera DE2-70 with Quartus II Free Web Edition.

I tried to build 3-Bit modulo 5 counter. However, the clock signal is not regenerate smoothly and the flip-flop logic seem different.Herewith I attach the picture of the signals. From bottom; D0 (GPIO_0[0]), D1 (GPIO_0[1]), D2 (GPIO_0[2]), D3 (GPIO_0[3]) and D7 (GPIO_0[7]) at top.

https://www.alteraforum.com/forum/attachment.php?attachmentid=7087

Its generate from .bdf, .v and .sdc

https://www.alteraforum.com/forum/attachment.php?attachmentid=7088

module bitmodulo5( 
    CLOCK_50,     
    GPIO_0,
    VCC
); 
input CLOCK_50; 
input VCC;
output  GPIO_0;
assign GPIO_0 = CLOCK_50;
assign GPIO_0 = VCC;
// Instantiation:
JKFF JKFF_inst
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
JKFF JKFF_inst1
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
    
JKFF JKFF_inst2
 (.j(GPIO_0), .k(GPIO_0),
   .clk(CLOCK_50), .clrn(GPIO_0), .prn(GPIO_0),
   .q(GPIO_0));
endmodule

#Constrain the base clock
create_clock -add -period 10.000 
             -waveform { 0.000 5.000 } 
             -name CLOCK_50 
             
# Constrain the divide by 2 register clock
create_generated_clock -add -source CLOCK_50 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
                 
create_generated_clock -add -source CLOCK_60 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
                 
create_generated_clock -add -source CLOCK_70 
             -name div2clock 
             -divide_by 2 
             -master_clock CLOCK_50 
             
report_ucp -summary

I know there is something wrong with my Clock Constraint. The execution done without error. Which part should I do to generate smooth clock and correct flip-flop logic? Thank you in advance!

Altera_Forum · ‎05-20-2013

I already figured out the answer for my question. There is a good example and tutorial on how to build a simple 3bit modulo counter :

http://hep-outreach.uchicago.edu/samples/3bit_counter/

The only problem is because I am using the free version therefore I cannot make the .vwf file. I am looking for the license and seem university license may help solving the problem.