problems simulating Full adder

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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

problems simulating Full adder

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I designed a full adder based on this video https://www.youtube.com/watch?v=k04b8b6kwri&t=366s in quartus 9.1 but for some reason im unable to produce a waveform like in the video and when ever I try I get XXXXXXXXXXXXX for bout sum and Count.

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