project compiled under 9.0sp1, doesn't under 9.1

[Altera_Forum]

have a project that pass's data from high speed serial link to a usb device. when i compile under 9.0sp1 the system works fine. compile under 9.1 and all though it has the appearance of working, i.e. passing data, the 'data is corrupted'. 

 anyone else had problems with 9.1?

[Altera_Forum]

--- Quote Start ---  have a project that pass's data from high speed serial link to a usb device. when i compile under 9.0sp1 the system works fine. compile under 9.1 and all though it has the appearance of working, i.e. passing data, the 'data is corrupted'.  anyone else had problems with 9.1?  --- Quote End ---    Hi,  did you get other Warnings .... Maybe the defaults settings are different ..  Kind regards  GPK

[Altera_Forum]

I think we need more info about the design. What IP cores are you using? Where do you think the problem lies? 

 Jake

[Altera_Forum]

haven't checked defaults, i'll check that. 

 i'm using altera wizard's registers and fifos, also altera library gates.   where i think the problem is? don't know. i did examine the rtl logic in data and control paths of both compilations and didn't see any differences.  sent it in to altera, but was curious if anyone else had seen this. dave

[Altera_Forum]

Sounds like (missing) timing constraints to me. Do you have EVERYTHING constrained? Some (most?) IP cores require some intervention (at minimum) to get proper results from Timequest...for both fitting and final timing analysis. 

 - slacker

[Altera_Forum]

had been running both 9.0 and 9.1 on same computer and ran into something real strange. so i removed all quartus programs and re-installed 9.0 on this machine. i had all ready loaded 9.1 on my laptop. i did a side-by-side compare of flags and setup and other than 9.1 has more (left on default) and 'parrellel synthesis' flag being on for 9.0, they were both the same. i then deleted both 'db' files and recompiled both. i compared 'sof' and 'jic' files of both 9.0 and 9.1, and they were different by wide margin. i tried 'parrellel synthesis' flag on and off for 9.1, but the 'sof' files compared the same. 

 i also compared the report files, for both, some were comparitively the same, others were very different. in fpga assets, 9.1 uses went up, over all, by ~10% (like registers went from 284 to 314).  timing is setup with global values. after all, this state machine runs at >> 25Mhz <<. (9.0 reported it couldn't make slow or fast mode and 9.1 reported it couldn't make fast mode).  i attached the report files (in one zip file), for anyone that would like to look at them. thanks d