Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

propagation delay

Altera_Forum
Honored Contributor II
3,501 Views

How to find the overall value of a circuit's propagation delay.A circuit having multiple inputs and outputs? 

 

I am using quartus 2 10.1 web edition.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
1,927 Views

 

--- Quote Start ---  

How to find the overall value of a circuit's propagation delay.A circuit having multiple inputs and outputs? 

 

I am using quartus 2 10.1 web edition. 

--- Quote End ---  

 

 

Hi, 

 

the question is not easy to answer, because the delay depends on the placement and the routing. The delay could not be less than the delay of the input anf the output cell. 

 

Kind regards 

 

GPK
0 Kudos
Altera_Forum
Honored Contributor II
1,927 Views

With Timing Analyzer, I think you can get the worst propagation delay time.

0 Kudos
Altera_Forum
Honored Contributor II
1,927 Views

If you just want to find out what the propagation delay is from an input(s) to an output(s) (assuming combinatorial logic only), then in TimeQuest you can use the following command: 

 

report_path -from <inputs> -to <outputs> 

 

If you want to actually constrain these paths, then use the set_max_delay and set_min_delay SDC constraints.
0 Kudos
Reply