quartus II libs

[Altera_Forum]

This might be a stupid question but, here goes. 

 How do I add a Library to the current quartus project, via the Library pane in settings? If so does the top directory denote the library name? example  lets say I have a directory structure as so;  /home/quartus/lib/A/B  if I place the path /home/quartus/A Will 'A' be the Library name for vhdl 'library' purposes? also will the contents of 'B' be added or ignored? Oh, what libs are added by default and where are they located under altera/libraries?   thanxs

[Altera_Forum]

User Libraries in Quartus are not VHDL libraries. The user library is just a directory that it will look in for source files. So after reading in all the explicitly specified source, you instantiate an entity called gremlin but there is no entity for it. Quartus will look in your libraries(directories) for any source files called gremlin, like gremlin.vhd, gremlin.v, etc. It won't read in all files in that directory, it just looks for the name. So the library is just a shortcut for adding files to the project. 

For a VHDL library, you need to manually add the file, then click on Properties and put in a name in the Library. The contents of that file will then be compiled into that library, which can then be accessed via LIBRARY and USE statements.  These are two different things that are unfortunately both called libraries. Hopefully that helps.

[Altera_Forum]

thanxs for your quick reply. 

 1.) for search for libs...I guess the libs pan under settings just gives a search path then correct? Does quartus look for file names or entities? in other words if I have a entity I try and instantiate does it look for the entity name as file name or does it read the files and look in them for a entity which matches?  are the ieee libs etc brought in by default or do I have to add files to project and then under properties specify which lib they will be available under?

[Altera_Forum]

File name only. It won't read the file if the name doesn't match. 

 IEEE is brought in by default.

[Altera_Forum]

Thanxs...only ieee is brought in?

[Altera_Forum]

I'm not sure what's brought in. I've never heard of any problems, i.e. it brings in all the ones people use, like 1164 and numeric_std. If there's something that isn't common, give it a try.

[Altera_Forum]

--- Quote Start ---  I'm not sure what's brought in. I've never heard of any problems, i.e. it brings in all the ones people use, like 1164 and numeric_std. If there's something that isn't common, give it a try.  --- Quote End ---    thank you for your help.

[Altera_Forum]

--- Quote Start ---  Thanxs...only ieee is brought in?  --- Quote End ---    the std library is also included (std.standard is implicitly included in ALL vhd files). The IEEE library mostly contains libraries that are part of the VHDL 93 standard (std_logic_signed/unsigned/arith/misc are NOT part of the VHDL standard, but Altera includes support for them due to many legacy designs that still use them).

[Altera_Forum]

--- Quote Start ---  File name only. It won't read the file if the name doesn't match.  IEEE is brought in by default.  --- Quote End ---    As far as Im aware, it looks for entity names, not just filenames (thats more a verilog thing). By default it will put everything in the work library unless you specify otherwise, but it's not as strict as the standard specifies when looking for entities in libraries. If it cannot find the entity in the work library, it will just look around until it finds it in any other library.  The library section doesnt apply to VHDL. Its more an AHDL throwback. AHDL has .inc files (like .h files in C) that cannot be included in the file list. An AHDL file may use include somefile.inc and Quartus will search through the libraries paths until it finds the .inc files.

[Altera_Forum]

Hi..I'm very confused now! What you say totally contradicts what the prior poster said. 

Could someone please clarify the situation?

[Altera_Forum]

--- Quote Start ---  Hi..I'm very confused now! What you say totally contradicts what the prior poster said. Could someone please clarify the situation?  --- Quote End ---    may be this thread will help:  http://www.alteraforum.com/forum/showthread.php?t=40756&highlight=vhdl+library

[Altera_Forum]

--- Quote Start ---  Hi..I'm very confused now! What you say totally contradicts what the prior poster said. Could someone please clarify the situation?  --- Quote End ---    If all your code is VHDL or verilog, you dont need to add anything in the libraries section, just add all the source files to the file list. You only really need the library section if you have AHDL.

[Altera_Forum]

--- Quote Start ---  may be this thread will help:  http://www.alteraforum.com/forum/showthread.php?t=40756&highlight=vhdl+library  --- Quote End ---     hi...thanxs for your help... I am beginning to understand, but what exactly is the library section of settings for then? I mean, let's say I have a few files with defined entities, can I place them in a directory and put the path in  library settings and quartus will pick them up and add them to 'work' lib? Sorta like a C include file for headers etc?

[Altera_Forum]

Yes. It's a Quartus-specific mechanism to point to a directory that has a lot of your files in it without explicitly adding each one. I prefer explicitly adding them, but is meant to make things easier.

[Altera_Forum]

--- Quote Start ---  Yes. It's a Quartus-specific mechanism to point to a directory that has a lot of your files in it without explicitly adding each one. I prefer explicitly adding them, but is meant to make things easier.  --- Quote End ---    I tried it...putting some files in a directory and defining a top level file then compiling. Best I can tell quartus does not even touch the files in the directory (i.e. the last access time does not change). What am I doing wrong?

[Altera_Forum]

--- Quote Start ---  Yes. It's a Quartus-specific mechanism to point to a directory that has a lot of your files in it without explicitly adding each one. I prefer explicitly adding them, but is meant to make things easier.  --- Quote End ---    Actually, Quartus does not pick up any VHDL files that are not explicity in the file list.  The libraries section is just a legacy thing to support AHDL.  The libraries section in the settings has nothing to do with VHDL libraries.  Basically, unless you are using AHDL, the libraries section is pretty useless.

[Altera_Forum]

--- Quote Start ---  Actually, Quartus does not pick up any VHDL files that are not explicity in the file list.  The libraries section is just a legacy thing to support AHDL.  The libraries section in the settings has nothing to do with VHDL libraries.  Basically, unless you are using AHDL, the libraries section is pretty useless.  --- Quote End ---     According to Rysc the following is true;  "What about explicitly adding the file/s? The libraries are only places for Quartus to look for design files that match the missing component name. For example, if your HDL instantiates a module/entity called blaa, Quartus will first look through all the files specificially added in Project -> Add Files to see if blaa is defined anywhere. If not, then it looks in the libraries for files that have that in the name, like blaa.v or blaa.vhd. It does not search all files, just known filetypes. It also won't look inside the files if the names don't match, so if you have a file called blaa_altera.v, which has a module called blaa inside, it won't look at that because the name doesn't match blaa. Just some ideas as to what might be happening. "  Does this have any validity at all?

[Altera_Forum]

In my experience with VHDL, Quartus will NOT search your libraries path for source files. All VHDL files MUST be in the file list (either directly, or a tcl file that picks up a file list from somewhere). I have no experience with Verilog on this issues, but I know that verilog has no libraries features built into the language, so it may search the directories in the libraries path for source files (verilog allows include files, like AHDL, whcih are probably pulled out of the library directories, because I know for AHDL you cannot include .inc files in the file list, they MUST be picked up from your libraries settings. Putting a .inc file in the file list causes a compile error because it is not a complete unit) 

 For VHDL, Quartus will only compile files in the file list. If you are using component instantiations, they are all treated as black boxes until the mapping stage. If the component cannot be mapped to an entity, it will not do any further compilations to try and find the entity or source file, it just throws an error. With direct instantiation, again, if the entity hasnt been compiled already, it will throw an error. Files in the libraries path are NOT compiled.  What exactly are you trying to do?

[Altera_Forum]

--- Quote Start ---  In my experience with VHDL, Quartus will NOT search your libraries path for source files. All VHDL files MUST be in the file list (either directly, or a tcl file that picks up a file list from somewhere). I have no experience with Verilog on this issues, but I know that verilog has no libraries features built into the language, so it may search the directories in the libraries path for source files (verilog allows include files, like AHDL, whcih are probably pulled out of the library directories, because I know for AHDL you cannot include .inc files in the file list, they MUST be picked up from your libraries settings. Putting a .inc file in the file list causes a compile error because it is not a complete unit)  For VHDL, Quartus will only compile files in the file list. If you are using component instantiations, they are all treated as black boxes until the mapping stage. If the component cannot be mapped to an entity, it will not do any further compilations to try and find the entity or source file, it just throws an error. With direct instantiation, again, if the entity hasnt been compiled already, it will throw an error. Files in the libraries path are NOT compiled.  What exactly are you trying to do?  --- Quote End ---     Sorry to be a pain! you've been a very big help. I'm just trying to learn the software before I start using it.

[Altera_Forum]

It does this for AHDL, VHDL, Verilog, .bdf(schematics), etc. Here's an example in VHDL that only adds the top-level and gets the sub-hierarchy through a library: 

set_global_assignment -name VHDL_FILE test.vhd set_global_assignment -name SEARCH_PATH .\\rtl\\user_lib  Note that there is also a message when it does this rather than read something explicit: Warning (12125): Using design file rtl/user_lib/basic_shift_register.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project  Info (12022): Found design unit 1: basic_shift_register-rtl  Info (12023): Found entity 1: basic_shift_register  (Also note that the project directory is a library by default even if not specified. So if your top-level in your .qsf is called "topmod" it will look in explicitly added files first. If it's not there, it will look in the project directory for any source files that are topmod, i.e. topmod.vhd or topmod.sv. This repeats for all entities. (It doesn't re-read explicitly added files. It actually reads all explicitly added files and creates a list of found modules/entities/etc. and only when something can't be found there does it look in libraries)

[Altera_Forum]

Ok - sorry for contradicting you RISC. I was convinced I have had problems using the libraries in the past, hence my posts. 

 To Drforbin - I would still recommend you explicitly add each source file to your project. This makes it more obvious what is part of the project and what is not.