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quartus crashes on case map

Altera_Forum
Honored Contributor II
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Check it out! I can crash Quartus v15 and v16.1 on two different computers! If I move my code around in the file, sometimes it completes sucessfully, sometimes it crashes hard. Mostly it crashes hard... (I should add I get identical crash whether I build with make or use the quartus IDE). >gmake /usr/local/altera/quartus/bin/quartus_map --read_settings_files=on --source=Main.vhd --source=DataMapper.vhd --source=DataMapperBytes.vhd --source=../BuildNumber.vhd --source=../../../../../include/xilinx/DnaRegisterAltera.vhd --source=../../../../../include/xilinx/IOBufP3Generic.vhd --source=../../../../../include/xilinx/IOBufP2Generic.vhd --source=../../../../../include/xilinx/ZBusAddrTx.vhd --source=../../../../../include/xilinx/VariableClockDivider.vhd --source=../../../../../include/xilinx/UartTxFifo.vhd --source=../../../../../include/xilinx/UartTx.vhd --source=../../../../../include/xilinx/UartRxRaw.vhd --source=../../../../../include/xilinx/UartRxParity.vhd --source=../../../../../include/xilinx/UartRxFifoParity.vhd --source=../../../../../include/xilinx/UartRxFifo.vhd --source=../../../../../include/xilinx/UartRx.vhd --source=../../../../../include/xilinx/SRamSlaveBus.vhd --source=../../../../../include/xilinx/SpiRegisters.vhd --source=../../../../../include/xilinx/SpiMaster.vhd --source=../../../../../include/xilinx/SpiBus.vhd --source=../../../../../include/xilinx/RtcCounter.vhd --source=../../../../../include/xilinx/RamBus.vhd --source=../../../../../include/xilinx/PPSCount.vhd --source=../../../../../include/xilinx/PhaseComparator.vhd --source=../../../../../include/xilinx/OneShot.vhd --source=../../../../../include/xilinx/ltc2378fifo.vhd --source=../../../../../include/xilinx/LpcArmBoot.vhd --source=../../../../../include/xilinx/IBufP3.vhd --source=../../../../../include/xilinx/IBufP2.vhd --source=../../../../../include/xilinx/gated_fifo.vhd --source=../../../../../include/xilinx/fifo_gen.vhd --source=../../../../../include/xilinx/fifo_fram.vhd --source=../../../../../include/xilinx/ClockDivider.vhd --source=../../../../../include/xilinx/ClockMultiplierAltera.vhd --source=../../../../../include/xilinx/SpiDac.vhd --source=/usr/local/altera/ip/altera/altchip_id/source/altchip_id.v --source=../../../../../include/xilinx/AdcClocks.vhd Brd457 Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition Info: Copyright (C) 2016 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Intel and sold by Intel or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Apr 26 12:06:26 2017 Info: Command: quartus_map --read_settings_files=on --source=Main.vhd --source=DataMapper.vhd --source=DataMapperBytes.vhd --source=../BuildNumber.vhd --source=../../../../../include/xilinx/DnaRegisterAltera.vhd --source=../../../../../include/xilinx/IOBufP3Generic.vhd --source=../../../../../include/xilinx/IOBufP2Generic.vhd --source=../../../../../include/xilinx/ZBusAddrTx.vhd --source=../../../../../include/xilinx/VariableClockDivider.vhd --source=../../../../../include/xilinx/UartTxFifo.vhd --source=../../../../../include/xilinx/UartTx.vhd --source=../../../../../include/xilinx/UartRxRaw.vhd --source=../../../../../include/xilinx/UartRxParity.vhd --source=../../../../../include/xilinx/UartRxFifoParity.vhd --source=../../../../../include/xilinx/UartRxFifo.vhd --source=../../../../../include/xilinx/UartRx.vhd --source=../../../../../include/xilinx/SRamSlaveBus.vhd --source=../../../../../include/xilinx/SpiRegisters.vhd --source=../../../../../include/xilinx/SpiMaster.vhd --source=../../../../../include/xilinx/SpiBus.vhd --source=../../../../../include/xilinx/RtcCounter.vhd --source=../../../../../include/xilinx/RamBus.vhd --source=../../../../../include/xilinx/PPSCount.vhd --source=../../../../../include/xilinx/PhaseComparator.vhd --source=../../../../../include/xilinx/OneShot.vhd --source=../../../../../include/xilinx/ltc2378fifo.vhd --source=../../../../../include/xilinx/LpcArmBoot.vhd --source=../../../../../include/xilinx/IBufP3.vhd --source=../../../../../include/xilinx/IBufP2.vhd --source=../../../../../include/xilinx/gated_fifo.vhd --source=../../../../../include/xilinx/fifo_gen.vhd --source=../../../../../include/xilinx/fifo_fram.vhd --source=../../../../../include/xilinx/ClockDivider.vhd --source=../../../../../include/xilinx/ClockMultiplierAltera.vhd --source=../../../../../include/xilinx/SpiDac.vhd --source=/usr/local/altera/ip/altera/altchip_id/source/altchip_id.v --source=../../../../../include/xilinx/AdcClocks.vhd Brd457 Info (20034): Auto device selection is not supported for MAX 10 device family. The default device, 10M08DAF484C8G, is set. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 2 design units, including 1 entities, in source file Main.vhd .... Info (12128): Elaborating entity "SpiBusPorts" for hierarchy "SpiRegistersPorts:SpiRegistersExt|SpiBusPorts:SpiBus" File: /home/steve/projects/zonge/firmware/include/xilinx/SpiRegisters.vhd Line: 108 Info (12128): Elaborating entity "DataMapperBytesPorts" for hierarchy "DataMapperBytesPorts:DataMapperExt" File: /home/steve/projects/zonge/firmware/457_ZenII/firmware/fpga/Main/Main.vhd Line: 1833 Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlstatement_elab.cpp, Line: 527 covered_old_implementation && covered_new_implementation || !covered_old_implementation && !covered_new_implementation Stack Trace: 0x311a1a: VhdlCaseStatement::AnalyzeCaseAlternatives(VhdlDataFlow*) + 0x5c8 (synth_vrfx) 0x3185fd: VhdlCaseStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x1af (synth_vrfx) 0x31995b: VhdlIfStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x555 (synth_vrfx) 0x31995b: VhdlIfStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x555 (synth_vrfx) 0x318e97: VhdlProcessStatement::Execute(VhdlDataFlow*, VhdlBlockConfiguration*) + 0x1cf (synth_vrfx) 0x2ba51e: VhdlArchitectureBody::Elaborate(VhdlBlockConfiguration*) + 0xfc (synth_vrfx) 0x2bae6d: VhdlEntityDecl::CoreElaborate(VhdlSecondaryUnit*, char const*, VhdlBlockConfiguration*) + 0x453 (synth_vrfx) 0x2c044c: VhdlEntityDecl::Elaborate(char const*, Array*, Map*, VhdlBlockConfiguration*) + 0x3f0 (synth_vrfx) 0x14f80c: VRFX_VERIFIC_VHDL_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0x1c8 (synth_vrfx) 0x1451a7: VRFX_ELABORATOR::elaborate(BASEX_ELABORATE_INFO*) + 0x97 (synth_vrfx) 0x178857: SGN_FN_LIB::elaborate(BASEX_ELAB_INFO_CORE*) const + 0x157 (synth_sgn) 0x1815ce: SGN_FN_LIB::start_vrf_flow() const + 0xe (synth_sgn) 0x181c24: SGN_FN_LIB::start(SGN_WRAPPER_INFO*) + 0x574 (synth_sgn) 0x1864f0: SGN_EXTRACTOR::single_module_extraction(HDB_INSTANCE_NAME*, HDB_ENTITY*, SGN_WRAPPER_INFO*) const + 0xf0 (synth_sgn) 0x18e2d8: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x1f8 (synth_sgn) 0x18f296: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist(HDB_ENTITY*, HDB_INSTANCE_NAME*, unsigned long, SGN_WRAPPER_INFO*) + 0x546 (synth_sgn) 0x18e3bc: SGN_EXTRACTOR::recursive_extraction(HDB_INSTANCE_NAME*, SGN_WRAPPER_INFO*, char const*) + 0x2dc (synth_sgn) 0x1945a3: SGN_EXTRACTOR::extract() + 0x3a3 (synth_sgn) 0x1a4f30: sgn_qic_full(CMP_FACADE*, std::vector&, std::vector&) + 0x440 (synth_sgn) 0x1c3b9: qsyn_execute_sgn(CMP_FACADE*, std::vector&, std::string const&, THR_NAMED_PIPE*, THR_NAMED_PIPE*) + 0x159 (quartus_map) 0x37d51: QSYN_FRAMEWORK::execute_core(THR_NAMED_PIPE*, THR_NAMED_PIPE*) + 0x231 (quartus_map) 0x3bcdc: QSYN_FRAMEWORK::execute() + 0xc4c (quartus_map) 0x1c75b: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x888 (comp_qexe) 0x3025c: qsyn_main(int, char const**) + 0x13c (quartus_map) 0x407e0: msg_main_thread(void*) + 0x10 (ccl_msg) 0x602c: thr_final_wrapper + 0xc (ccl_thr) 0x4089f: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg) 0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem) 0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 0x63f2: thr_thread_wrapper + 0x15 (ccl_thr) 0x42c37: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg) 0x21f45: __libc_start_main + 0xf5 (c.so.6) End-trace gmake: *** [Brd457.map.rpt] Error 2 Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! >Exit code: 2

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Altera_Forum
Honored Contributor II
309 Views

TO_BE_DONE

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Altera_Forum
Honored Contributor II
309 Views

A crash can only really be diagnosed by altera - raise a mysupport ticket. 

Have you tried deleting the db and incremental_db folders and trying again>?
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Altera_Forum
Honored Contributor II
309 Views

 

--- Quote Start ---  

A crash can only really be diagnosed by altera - raise a mysupport ticket. 

Have you tried deleting the db and incremental_db folders and trying again>? 

--- Quote End ---  

 

 

I tried the "clean" -> "all revisions" menu option which has no effect on the bug. 

 

It seems I am unable to "raise a mysupport ticket" see the attached graphic - it's all greyed out!
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