quartus_map fails with "17942 No Open project exsists" after adding probes

[Altera_Forum]

I have a design with a couple of hundred probes. 

At some point I make a change to the signal tap signal list. After that change I get the following error message : Error (17942): No open project exists Followed by lots of other messages. Reversing the latest change doesnt fix the problem. The most relaiable way to resolve the problem is to copy the whole design into a new directory and create a new project file. Its costing me days each time this happens.  Here is a more complete log of the error messages :    Info: Running Quartus Prime Analysis & Synthesis  Info: Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition  Info: Processing started: Tue Sep 12 13:48:37 2017 Info: Command: quartus_map --parallel=1 --helper=4 --helper_type=user_partition --partition=sld_signaltap:auto_signaltap_1 TRUSTREAM_FPGA -c TRUSTREAM_FPGA Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error: Quartus Prime Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings  Error: Peak virtual memory: 1843 megabytes  Error: Processing ended: Tue Sep 12 13:48:55 2017  Error: Elapsed time: 00:00:18  Error: Total CPU time (on all processors): 00:00:17 Error: Quartus Prime Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings  Error: Peak virtual memory: 1872 megabytes  Error: Processing ended: Tue Sep 12 13:48:55 2017  Error: Elapsed time: 00:00:18  Error: Total CPU time (on all processors): 00:00:18 Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists Error (17942): No open project exists  Info (284007): State machine "|FF7_PCIE|DDR_NODE:DDR_NODE_inst_0|ring_fifo_to_mem:ring_fifo_to_mem_0|state" will be implemented as a safe state machine. Info (284007): State machine "|FF7_PCIE|DDR_NODE:DDR_NODE_inst_0|ring_if:ring_if|StrRdBuf_state" will be implemented as a safe state machine. Error: Quartus Prime Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings  Error: Peak virtual memory: 2083 megabytes  Error: Processing ended: Tue Sep 12 13:50:06 2017  Error: Elapsed time: 00:01:29  Error: Total CPU time (on all processors): 00:01:29 Info (19000): Inferred 2 megafunctions from design logic  Info (276029): Inferred altsyncram megafunction from the following design logic: "DDR_NODE:DDR_NODE_inst_0|ring_fifo_to_mem:ring_fifo_to_mem_0|mc_input_buffers:mc_input_buffers|fifo_N:CmdFifo|f_memory_rtl_0"   Info (286033): Parameter OPERATION_MODE set to DUAL_PORT  Info (286033): Parameter WIDTH_A set to 297  Info (286033): Parameter WIDTHAD_A set to 9  Info (286033): Parameter NUMWORDS_A set to 512  Info (286033): Parameter WIDTH_B set to 297  Info (286033): Parameter WIDTHAD_B set to 9  Info (286033): Parameter NUMWORDS_B set to 512  Info (286033): Parameter ADDRESS_ACLR_A set to NONE  Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED  Info (286033): Parameter ADDRESS_ACLR_B set to NONE  Info (286033): Parameter OUTDATA_ACLR_B set to NONE  Info (286033): Parameter ADDRESS_REG_B set to CLOCK1  Info (286033): Parameter INDATA_ACLR_A set to NONE  Info (286033): Parameter WRCONTROL_ACLR_A set to NONE  Info (286033): Parameter RAM_BLOCK_TYPE set to M20K  Info (276029): Inferred altsyncram megafunction from the following design logic: "DDR_NODE:DDR_NODE_inst_0|ring_fifo_to_mem:ring_fifo_to_mem_0|mc_output_buffers:mc_output_buffers|fifo_N:RespFifo|f_memory_rtl_0"   Info (286033): Parameter OPERATION_MODE set to DUAL_PORT  Info (286033): Parameter WIDTH_A set to 307  Info (286033): Parameter WIDTHAD_A set to 8  Info (286033): Parameter NUMWORDS_A set to 256  Info (286033): Parameter WIDTH_B set to 307  Info (286033): Parameter WIDTHAD_B set to 8  Info (286033): Parameter NUMWORDS_B set to 256  Info (286033): Parameter ADDRESS_ACLR_A set to NONE  Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED  Info (286033): Parameter ADDRESS_ACLR_B set to NONE  Info (286033): Parameter OUTDATA_ACLR_B set to NONE  Info (286033): Parameter ADDRESS_REG_B set to CLOCK1  Info (286033): Parameter INDATA_ACLR_A set to NONE  Info (286033): Parameter WRCONTROL_ACLR_A set to NONE  Info (286033): Parameter RAM_BLOCK_TYPE set to M20K Error (12154): Can't elaborate inferred hierarchy "DDR_NODE:DDR_NODE_inst_0|ring_fifo_to_mem:ring_fifo_to_mem_0|mc_input_buffers:mc_input_buffers|fifo_N:CmdFifo|altsyncram:f_memory_rtl_0" Error: Quartus Prime Analysis & Synthesis was unsuccessful. 7 errors, 2 warnings  Error: Peak virtual memory: 2297 megabytes  Error: Processing ended: Tue Sep 12 13:50:11 2017  Error: Elapsed time: 00:01:34  Error: Total CPU time (on all processors): 00:01:33 Error (281039): Finished parallel synthesis of 0 partition(s). 4 partitions did not finish parallel synthesis because there were errors  Error (281040): Partition "sld_signaltap:auto_signaltap_0" did not complete synthesis due to errors  Error (281040): Partition "Top" did not complete synthesis due to errors  Error (281040): Partition "sld_signaltap:auto_signaltap_1" did not complete synthesis due to errors  Error (281040): Partition "sld_hub:auto_hub" did not complete synthesis due to errors Info (144001): Generated suppressed messages file /mnt/NFS/Storage/Rene/FF40/FF40_008_0825_3_No_PTP_2/output_files_stp2/TRUSTREAM_FPGA.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 50 errors, 294 warnings  Error: Peak virtual memory: 4071 megabytes  Error: Processing ended: Tue Sep 12 13:50:38 2017  Error: Elapsed time: 00:10:22  Error: Total CPU time (on all processors): 00:13:06 Error (293001): Quartus Prime Full Compilation was unsuccessful. 52 errors, 294 warnings

[Altera_Forum]

Instead of copying the project over to a new directory, have you tried simply disabling, at least temporarily, Signal Tap from the project Settings? If you can synthesize the design without Signal Tap, then something is messed up in your .stp file. Are you trying to tap pre-synthesis or post-fit nodes? In most cases that I've found, pre-synthesis is the way to go.

[Altera_Forum]

I saw something where someone got the same messages. 

1) They were able to get around it by turning off Parallel Synthesis. 2) It supposedly was fixed in Q16.1 So those are two things to try.

[Altera_Forum]

--- Quote Start ---  Instead of copying the project over to a new directory, have you tried simply disabling, at least temporarily, Signal Tap from the project Settings? If you can synthesize the design without Signal Tap, then something is messed up in your .stp file. Are you trying to tap pre-synthesis or post-fit nodes? In most cases that I've found, pre-synthesis is the way to go.  --- Quote End ---    Yes I have, without success.  The suggestion by Rysc works : 1) They were able to get around it by turning off Parallel Synthesis. I run Analysis & Synthesis with only 1 CPU. After that I can change back to using all available CPU's again. I can continue with fitter, or run from Analysis & Synthesis. I dont need to change any probes.  It seems to me that the database is corrupted and by running Analysis & Synthesis with 1 CPU the error in the database is corrected.   

[Altera_Forum]

I have build quartus 6.1.2 and ran into the same problem. 

After integrating another module into the design, the build fails almost every time. The only way I can build reliably is by doing a Project->Clean Project and build with 1 CPU only. This results in a build time that is doubled.