quartus netlist file generation

[Altera_Forum]

Hi there 

 I am developing an SOPC component and want to give it to my partners for testing. But as we are in an early development stage, I do not want to give them the VHDL code. Is far as I have researched, a post-synthesis netlist file would be perfect for this purpose.   Is this the right approach for this problem - and if yes - can quartus generate such file and how do I get it?  thanks in advance  Stonie

[Altera_Forum]

I would give my partner the VHDL. 

 But if you're sure you want what you're asking for then try... quartus_map (project) quartus_cdb --vqm=(project).vqm (project) put the VHDL file somewhere safe, use the VQM source instead.  It may well not work. The SOPC builder most likely knows things about the component like the bus port interface, parameters, etc. which will not hold on a synthesis cell netlist.