Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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question about set_input_delay

Altera_Forum
Honored Contributor II
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The following list describes the options for the set_input_delay command, anybody tell me when shall we specify the -rise|-fall option? 

-clock <clock name> Specifies the source clock. -clock_fall Specifies the arrival time with respect to the falling edge of the clock. -rise | -fall Specifies either the rise or fall delay at the port. -max | -min Specifies the minimum or maximum data arrival time. -add_delay Adds another delay, but does not replace the existing delays assigned to the port. -reference_pin <target> Specifies a pin or port in the design from which to determine source and network latencies. This is useful to specify input delays relative to an output port fed by a clock. -source_latency_ included Specifies that the input delay value includes the source latency delay value, and therefore any source clock latency assigned to the clock will be ignored. <delay value> Specifies the delay value. <targets> Specifies the destination ports or pins.
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Altera_Forum
Honored Contributor II
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You could have different rise/fall times outside the part. For example, you could have an external -max -rise of 3.0ns and -max -fall of 2.9ns, or something like that. To be honest, I've seen a lot of complex constraints and have still never used these options.

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Altera_Forum
Honored Contributor II
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Thanks for your quick response...

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