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"21'b0" Verilog to VHDL explination please

Altera_Forum
Honored Contributor II
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Hello 

 

In Verilog I got this code: 

cont <= 21'b0; 

oRST <= 1'b1; 

 

What does it mean in VHDL?
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Altera_Forum
Honored Contributor II
662 Views

 

--- Quote Start ---  

Hello 

 

In Verilog I got this code: 

cont <= 21'b0; 

oRST <= 1'b1; 

 

What does it mean in VHDL? 

--- Quote End ---  

 

 

In VHDL const would have to have 21 bits, eg., 

 

signal const : std_logic_vector(20 downto 0); 

 

and you'd assign all zeros to it using 

 

const <= (others => '0'); 

 

The signal oRST is a 1-bit signal, eg., 

 

signal oRST : std_logic; 

 

and you'd assign a 1 to it via 

 

oRST <= '1'; 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
662 Views

Thanks! 

 

Now I have in VHDL: 

cont <= "000000000000000000000"; 

oRST <= '1'; 

 

:)
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Altera_Forum
Honored Contributor II
662 Views

 

--- Quote Start ---  

Now I have in VHDL: 

cont <= "000000000000000000000"; 

--- Quote End ---  

 

It's O.K. if you love it long-winded. 

 

You'll notice, that in Verilog also  

cont <= 0; 

is accepted as legal code, but giving a warning about assigning a 32 bit value to a 21 bit signal or something like that.  

 

In VHDL, the assigned constant must have the correct bit length if not using special constructs like OTHERS =>.
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