"ARCTAN" Function's Issue

Altera_Forum · ‎09-10-2013

Hi bros, this is my VHDL code to implement an "ARCTAN" function:

-- This is my code --

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.MATH_REAL.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.numeric_std.ALL;

USE ieee.std_logic_signed;

USE ieee.std_logic_unsigned;

ENTITY arctan IS

GENERIC (NUMBER_BIT: INTEGER:=16);

PORT

(

clk: IN STD_LOGIC;

reset: IN STD_LOGIC;

data_inI: IN STD_LOGIC_VECTOR(NUMBER_BIT-1 DOWNTO 0);

data_inQ: IN STD_LOGIC_VECTOR(NUMBER_BIT-1 DOWNTO 0);

arc_out: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)

);

END arctan;

ARCHITECTURE bhv OF arctan IS

BEGIN

PROCESS(clk,reset)

VARIABLE real_val1: REAL :=0.0;

VARIABLE real_val2: REAL :=0.0;

VARIABLE temp : REAL := 0.0;

BEGIN

IF (reset='0') THEN

arc_out<=(OTHERS=>'0');

ELSE IF(clk'EVENT AND clk='1') THEN

---convert STD_LOGIC type to REAL type----------

real_val1:= CONV_INTEGER(SIGNED(data_inI))**0.00003052; --1/(2^15)=1/32768=0.00003052

real_val2:= CONV_INTEGER(SIGNED(data_inQ))**0.00003052;

--------------------------------------------------

temp:=ARCTAN(real_val1,real_val2);

arc_out<= CONV_STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(temp*32768.0),6));

END IF;

END PROCESS;

END bhv;

-- End of my code --

And when I tried to compile it with Modelsim-Altera Starter Edition 10.0, I got a message as shown below:

Can you help me to solve this issue? Thank you so much.

Altera_Forum · ‎09-11-2013

You are including too many libraries. Those two are in direct conflict:USE ieee.std_logic_signed; USE ieee.std_logic_unsigned;The first one says you will want to do arithmetic directly on std_logic_vectors, using them as signed values, while the other one says you will use them as unsigned values. But both are non standard, so you should better remove them entirely.

Then, as the error message suggests, both those libraries

USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.numeric_std.ALL;

define a SIGNED type, so you should keep only one of them. I recommend to keep ieee.numeric_std.all, which is the only standard one.

So as a result, use only those libraries in your code:

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE IEEE.numeric_std.ALL;

And then fix the remaining errors that you get, mostly with the CONV functions that aren't defined any more. You can use the SIGNED type instead, and use the to_integer and to_signed functions for conversions.

Are you writing this just for simulating, or also to synthesize and put in an FPGA? The functions from MATH_REAL and the real types can't be synthesized.