Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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"case statement choices must cover all possible values of expression."


I am attempting to build the project 'qts_ddr4_x72_1200MHz' that is included in the download for the Arria 10 GX Dev Kit, using Quartus Pro 18.1 on Linux.


It fails at the synthesis stage with the following error:


Error(13630): VHDL Case Statement error at product_info.vhd(51): case statement choices must cover all possible values of expression. 'Others' clause is needed.


Here product_info.vhd is part of Platform Designer instantiated IP that is included in the project.


The weirdest part is that, as far as I can tell (I'm not familiar with VHDL), all possible values _are_ covered. The relevant code is:


      av_address : in std_logic_vector(1 downto 0);


            case av_address is

               when "00" => av_data_read <= product;

               when "01" => av_data_read <= board;

               when "10" => av_data_read <= sof;

               when "11" => av_data_read <= version;

            end case;



I saw this with and with It looks like a bug to me. Any ideas?

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2 Replies
Honored Contributor III

With VHDL std_logic_vector type, there are other levels besides 0 and 1, mostly used for simulation.


I'm guessing that the code included in the download for the dev kit is from an older version of the software. Pro edition synthesis is stricter than the standard edition on certain things and this might be part of that if this older code was designed for Standard edition (Arria 10 is the only device family supported in both Standard and Pro). You could either try editing the code (when OTHERS => av_data_read <= product;) or try compiling in the Standard edition of the software.


Yes, that edit takes care of the error, thanks.

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