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Hi, I'm new to verilog.
I was trying to use a counter to automatically reset the LCD after a period of time. my code for reset is as follows module Reset_Delay(clock, reset); input clock; output reg reset; reg [25:0] count; always at(forum doesn't allow me to use the symbol sorry:() (posedge clock) begin if (count < 20'hFFFFF) begin count <= count + 1; reset<= 1'b1; end else if (count < 'h1FFFFF) begin count <= count + 1; reset<= 1'b0; end else count <= 0; end endmodule there's nothing shown on the LCD. I tried using KEY for reset and it works find so I'm pretty sure it has nothing to do with other parts of the code. Thank you in advance! well after I accidentally changed the code to this: module Reset_Delay(iCLK,oRESET); input iCLK; output reg oRESET; reg [25:0] count; always at (posedge iCLK) begin if (count < 20'hFFFF) begin count <= count + 1; oRESET <= 1'b0; end else begin count <= count + 1; oRESET <= 1'b1; end end endmodule it works! but I have no idea why:(((( I didn't set count to 0, how would it keep changing?Link Copied
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You are asking count to go up when count < FFFF and also when it is not <FFFF. So it goes up freely and wraps back to zero and up again.
If you want to go up to FFFF and stay there then delete the second count statement but watch your count is not optimised off by a hostile compiler.
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