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Valued Contributor III
1,830 Views

running timing analysis without fitter first

Hi, 

 

whenever i initiate TimeQuest quartus seem to start by default the Fitter...is that a default operation or something is wrong in my project? I guess it should be feasible to just run synthesis and then timing analysis for a first estimation of clock speed 

 

Thanks
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Valued Contributor III
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On older device families (before the generation 10 devices, I believe), you can just synthesize your design, then manually select to create a post-map timing netlist in TimeQuest. On newer devices, I think you have to run the Fitter first all the time.

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Valued Contributor III
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In new device families (arria10 stratix10 ) you have at least to run the plan phase

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Valued Contributor III
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What to do when the project was build by a script: i.e. OpenCL project build script? When I try to run timing analyzer it still gives this error: "ERROR: Can't run TimeQuest Timing Analyzer (quartus_sta) -- Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully before running the TimeQuest analyzer (create_timing_netlist)." Is there a way to still run timing analysis for example to re-write our base.sdc constraints?

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Valued Contributor III
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OpenCL timing is all handled by the BSP. Are you creating a custom BSP?

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Valued Contributor III
104 Views

 

--- Quote Start ---  

OpenCL timing is all handled by the BSP. Are you creating a custom BSP? 

--- Quote End ---  

 

 

Yes, we have. Our company has integrated our IP with Intel OpenCL BSP of a10_ref but with 2 banks of DDR4. I would not be brave to say that the timing is handled by BSP though. We have a custom flow where we specify the timing of our IP and OpenCL kernels. BTW the timing has changed a lot from 16.x to 17.x tools for the better.
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