I use s10 fpga , and the compiler is quartus22.4 , in my design , I use a fpll as transceiver pll , but the fpll can not lock ， but when I use quartus21.1 to compile , fpll get locked .
I use quartus 22.4 because quartus21.1 will crash when transceiver channels more then 4 channels ,
If any one can help me ，or any one can get fpll locked in quartus 22.4
Attached is my project
This question you can reference below link , I post it and FPLL still not locked in quartuspro 22.4
note : Quartus version that I use are quartuspro22.4 & quartuspro21.1
I found the problem to be related to cascading of the IOPLL to the FPLL. For the S10 devices, this arrangement is not allowed. Please refer to the documentation links below:
This is also clearly visible from the RTL Netlist Viewer against Technology Map Viewer. The RTL viewer is the logic that you intend, whereas the Technology Map viewer is the design that you get.
So transceiver fpll (FPLL1) can use another cascade fpll (FPLL2) as reference source ,
if this is true , Can FPLL2 's reference clock source from IOPLL like below,
In my real design , IOPLL will change , so I wish when IOPLL change ,
the transceiver output data rate will auto changed also.
I will try the reference clk direct from differential pair , but it will limited my design ,
by the way , The same project processed by Quartuspro 21.1 work well , fpll can get locked , and function is correct，
so I think there is a way form IOPLL to FPLL, may be different Quartus version process the design different way .
I helped Ashlesha to see whether can get the fpll lock in our board for Q21.1.
However, we have problem to see the fpll can lock in the signal tap in Q21.1 as you said. Can you share the snapshot of the signal for "isp_fpga_clk_locked" in Q21.1?
Another thing is, we would like to try using simulator tools to see if we can see the waveform from the fpll locked. Do you have the testbench file (.tb) so that I can check the signal from the simulator?
Appreciate the snapshot provided.
Do you have the time to help us creating the .tb file from your design to simulate that signal? If you can't, then it's okay. Just let me know.
The internal team ask for the confirmation on below situation that you faced:
- 21.1, 4 transceiver channels - crash with internal error
- 21.1, <4 transceiver channels - can compile, fpll can lock
- 22.4, 4 transceiver channels - can compile, fpll cannot lock
- 22.4, <4 transceiver channels - can compile, fpll cannot lock
Is it accurate?
I modify first 2 item as below
- 21.1, >4 transceiver channels - crash with internal error
- 21.1, =<4 transceiver channels - can compile, fpll can lock
Above case is that , fpll's source is from io_pll
and if I use differential clk as fpll'a source , Q22.4's fpll will locked
So, to make it simpler, this is what we got from your explanation as below. Can you help to see each one of the scenarios and confirm if it is accurate or not?
- 21.1, fpll's source = iopll, >4 transceiver channels - crash with internal error
- 21.1, fpll's source = iopll, =<4 transceiver channels - can compile, fpll can lock
- 22.4, fpll's source = differential clk, >4 transceiver channels - can compile, fpll can lock
- 22.4, fpll's source = iopll, >4 transceiver channels - can compile, fpll cannot lock
- 22.4, fpll's source = differential clk, =<4 transceiver channels - can compile, fpll can lock
- 22.4, fpll's source = iopll, =<4 transceiver channels - can compile, fpll cannot lock
Thank you so much for your help to verify the scenarios you faced.
The engineering team is now investigating this issue, and it may take some time.
Really appreciate your understanding. I will update back to you once got any updates from them.
It seems that this case have take quite some time now.
Is it okay if I contact you by email if I have the updates from the engineering team regarding this issue?
As for now it seems will take some more time for them to focus on this. I really apologies for this and I appreciate your understanding.
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