sdc constraint Warning with altera_reserved_tck

Altera_Forum · ‎03-23-2011

Hi,

I have a design using Timequest. Suggested by altera website(rd04282008_867), I write this

constraint in .sdc file: create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}

After compiled the design, I received warnings below:

--- Quote Start ---

Warning: At least one of the filters had some problems and could not be matched.

Warning: altera_reserved_tck could not be matched with a port.

Warning: Ignored assignment: create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]

Warning: Argument <targets> is an empty collection

--- Quote End ---

Some info before these warnings:

Info: Starting physical synthesis optimizations for speed

Info: Fitter is using the TimeQuest Timing Analyzer

Info: Reading SDC File: 'Optimization.sdc'

I wonder whether I need to change some settings? Can anyone make suggestions? thx.

Altera_Forum · ‎03-23-2011

Does the clock show up in Report Unconstrained Paths?

Note that the JTAG clock now has a clock constraint embedded in it's RTL, so you generally don't have to do this anymore. I assume you're doing it to fix a problem, but not sure what the problem is.

Altera_Forum · ‎03-24-2011

I checked Report Unconstrained Paths, and I found out I made a foolish mistake.

As I changed the design, the node specified in signal tap became invalid. As a result, tck is not used in my design. After I fixed .stp file, the warning is solved.

Thanks for your advice