sdram tunning

[Altera_Forum]

hi  

I use EP2C20Q240C8 with a 32 bit sdram  when I use pll number 2 (pin 177 is pll_out that connected to sdram clock and pin 178 is  connected to sdram clock enable . Nios 2 program  is verified but the program doesn't execute .In the  other case when I use pll number 4 and sdram clock  is pin 177 and sdram clock enable is pin 178 Nios 2  program execute .Why the pll number 2 doesn't  work.I test this problem for variety of pll phase shift.

[Altera_Forum]

Is your I/O interface properly constrained?

[Altera_Forum]

for pll number 2 I connect clock to pin 152 and for pll 4 clock is connected 

to pin 91 the pins between sdram and cyclone 2 are the same as in two situation that described.

[Altera_Forum]

Sorry that's not what I meant. You need to give Quartus some timing constraints, either as assignments if you use the classic timing analyser, or in a sdc file if you are using TimeQuest. 

If you don't give any timing constraints, you can end up with an interface that works in some cases, and doesn't in others, depending on how the design was fitted in the FPGA.

[Altera_Forum]

tsu = 7.95 n tco_min = 1.33 n tco_max = 7.74 n th = -7.6 n  

these parameters are for pins that connected to sdram thanks for your help

[Altera_Forum]

Are these the values from the datasheet? Are you using the classic analyser or TimeQuest?

[Altera_Forum]

These data are from classic timing analizer after compiling a project that execute on my board.

[Altera_Forum]

You should really do it the other way round... Extract the required timing values from your SDRAM datasheet, input them as assignments, and let Qurtus' fitter use them to optimize the routing. Quartus will also tell you at the end if the timing requirements are met or not.

[Altera_Forum]

when i connect clock to pin 91(and therefor use pll number 4 )and no constrain on timing parameters(tsu, tco, tpd,th) with tsu=7.9 n  

tco_max=6.8 n tco_min=1.39 n th=-7.6 n my program on the board is executed. when i connect clock to pin 152 (and therefor use pll number 2) and  constrain on timing parameter with tsu=5.1 n tco_max=2.3 n tco_min = 1.53 n , th=-4.8 n my program isn't executed. timing parameter in the second case is beter from the first case but program  in the second case isn't executed . in the all situation clock=27mhz sdram_clock = 81mhz . if timing parameter cause this problem in first situation my program on the board dosn't execute.

[Altera_Forum]

I meet the same proble use EP2C20Q240C8. I did many work for this problem. 

1. I repeat design my PCB board, make the SDRAM signal very good. 2. I do timing constrained. caulation tsu, tco_min, tco_max etc. modify my SOPC etc.  Now, I aslo not solve this problem.   By the way, I didn't meet this problem use EP2C8/EP1C6/EP2C20F484/EP2C70 chip. so i think this is bug of EP2C20Q240C8 chip.

[Altera_Forum]

Hi 

I had the same problems with the PLL on the EP2C20Q240C8 chip. Has anyone got the PLL working stably on that chip?? Thanks

[Altera_Forum]

hi  

I solve this problem with change the pll in ep2c20q240c8 this down with changing the clock input.

[Altera_Forum]

Hi jamshid 

Did u change the clock input to be in the same bank as that of the PLL output? Thanks

[Altera_Forum]

hi 

you must change the clock in the other bank.

[Altera_Forum]

--- Quote Start ---  hi  you must change the clock in the other bank.  --- Quote End ---    Which PLL on the chip are u sing..if it is PLL2, did u put the clock to be pin 154 and the PLL output to be 177?  Thanks

[Altera_Forum]

hi  

I can't work with pll number 2 . I put the clock to pin 91 and sdram clock to pin 177.